Memory bypass function for a memory

Patent metadata

Field	Value
Publication number	US-10650906-B2
Application number	US-201816059477-A
Country	US
Kind code	B2
Filing date	Aug 9, 2018
Priority date	Aug 9, 2018
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.

First claim

We claim:

1. A memory bypass circuit for a memory device, comprising:
a word line disable circuit; and
a read and write activation circuit;
wherein the word line disable circuit is coupled to a word line of the memory device, and
wherein the read and write activation circuit is coupled to the memory device for concurrent activation of writing and reading functions of the memory device during a testing mode.

2. The memory bypass circuit of claim 1 further comprising an internal clock generator and a write data input circuit, wherein the internal clock generator is coupled to the word line disable circuit and the read/write activation circuit, and wherein the write data input circuit is coupled to a write driver of the memory device for providing test data.

3. The memory bypass circuit of claim 1 wherein the word line disable circuit comprises:
a latch,
an inverter,
a first AND gate for generating a word line deactivation signal A_C, and
a second AND gate for generating a word line deactivation signal A_T,
wherein inputs of the first AND gate are coupled to an output of the inverter, a negated logic test signal, and an internal clock signal, and
wherein inputs of the second AND gate are coupled to the negated logic test signal, the internal clock signal, and an output of the latch.

4. The memory bypass circuit of claim 3 wherein an input of the latch is coupled to an address input, wherein a clock input of the latch is coupled to an inverse of the internal clock signal, and wherein the word line deactivation signal A_C and the word line deactivation signal A_T are complimentary signals.

5. The memory bypass circuit of claim 1 wherein the read and write activation circuit comprises:
a latch,
an inverter,
a first NAND gate,
a second NAND gate,
a first OR gate for generating a write command signal, and
a second OR gate for generating a read command signal.

6. The memory bypass circuit of claim 5 wherein a first input of the first OR gate is coupled to the logic test signal and a second input of the first OR gate is coupled to an output of the first NAND gate, and wherein a first input of the second OR gate is coupled to the logic test signal and a second input of the second OR gate is coupled to an output of the second NAND gate.

7. The memory bypass circuit of claim 6 wherein the latch, the inverter, and the first NAND gate are serially connected for generating a signal indicative of a normal write command, and wherein the latch and the second NAND gate are serially connected for generating a signal indicative of a normal read command.

8. The memory bypass circuit of claim 1 wherein the internal clock generator comprises an OR gate, an AND gate, and an array-tracking timing delay.

9. The memory bypass circuit of claim 8 wherein a logic test signal and a negated chip enable signal are coupled to the OR gate, wherein an output of the of the OR gate, a clock signal, and an output of the array-tracking timing delay are coupled to inputs of the AND gate, wherein an output of the AND gate 182 provides for an internal clock signal, and wherein the output of the AND gate 182 is coupled to an input of the array-tracking timing delay.

10. The memory bypass circuit of claim 1 wherein the write data input circuit comprises:
a first XNOR gate having inputs for a data input, a bit-write signal, and a logic test signal,
a second XNOR gate having inputs for the data input, the bit-write signal, and the logic test signal,
a first latch, and
a second latch,
wherein the second XNOR gate is configured to provide a complementary output signal to an output of the first XNOR gate,
wherein an input of the first latch is coupled to the output of the first XNOR gate for generating a data signal D_T, and
wherein an input of the second latch is coupled to the output of the second XNOR gate for generating a complementary data signal D_C.

11. The memory bypass circuit of claim 10 wherein clock inputs of the first latch and the second latch are coupled to the read and write activation circuit for receiving a write signal.

12. A method for providing a write through function for a memory device, comprising:
disabling word line activation;
concurrently activating read and write functions of the memory device;
generating an internal clock signal for the concurrently activated read and write functions; and
providing known data to the memory device for writing to bit lines of the memory device during a testing mode.

13. The method of claim 12 wherein the word line activation disabling is based on a logic test signal, an address of a word line for disabling, and an internal clock signal.

14. The method of claim 12 wherein the read and write functions are concurrently activated based on a logic test, a read/write enable signal to indicate a normal function call, and an internal clock signal.

15. The method of claim 12 wherein the internal clock signal generation is based on the logic test signal, a chip enable signal, and a clock signal for the memory device.

16. The method of claim 12 wherein the provided known data, a bit-write signal, and a logic test signal are gated by at least one XNOR gate to generate a data signal to be written to the bit lines of the memory device.

17. A memory system, the system comprising:
a memory; and
a memory bypass circuit, wherein the memory bypass circuit comprises:
a word line disable circuit;
a read and write activation circuit;
a internal clock generator; and
a write data input circuit,

wherein the word line disable circuit is coupled to a word line of the memory device,
wherein the read and write activation circuit is coupled to the memory device for concurrent activation of writing and reading functions of the memory device during a testing mode,
wherein the internal clock generator is coupled to the word line disable circuit and the read/write activation circuit, and
wherein the write data input circuit is coupled to a write driver of the memory device for providing test data.

18. The memory system of claim 17 wherein the word line disable circuit comprises:
a latch,
an inverter,
a first AND gate for generating a word line deactivation signal A_C, and
a second AND gate for generating a word line deactivation signal A_T,
wherein inputs of the first AND gate are coupled to an output of the inverter, a negated logic test signal, and an internal clock signal,
wherein inputs of the second AND gate are coupled to the negated logic test signal, the internal clock signal, and an output of the latch,
wherein an input of the latch is coupled to an address input,
wherein a clock input of the latch is coupled to an inverse of the internal clock signal, and
wherein the word line deactivation signal A_C and the word line deactivation signal A_T are complimentary signals.

19. The memory system of claim 17 wherein the read and write activation circuit comprises:
a latch,
an inverter,
a first NAND gate,
a second NAND gate,
a first OR gate for generating a write command signal, and
a second OR gate for generating a read command signal,
wherein a first input of the first OR gate is coupled to the logic test signal and a second input of the first OR gate is coupled to an output of the first NAND gate,
wherein a first input of the second OR gate is coupled to the logic test signal and a second input of the second OR gate is coupled to an output of the second NAND gate,
wherein the latch, the inverter, and the first NAND gate are serially connected for gen

Assignees

• Synopsys Inc

Inventors

• Barth Jr John Edward
• Gorman Kevin W
• Pilo Harold

Classifications

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/1201

  comprising I/O circuitry · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C29/36

  Data generation devices, e.g. data inverters · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title