Interface level-shifter dual-rail memory architecture

Patent metadata

Field	Value
Publication number	US-12340864-B2
Application number	US-202318107450-A
Country	US
Kind code	B2
Filing date	Feb 8, 2023
Priority date	Feb 11, 2022
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry. The clock signal generation circuitry receives a first clock signal and an isolation signal, and generates a second clock signal based on the first clock signal and the isolation signal. The isolation signal corresponds to a power state of a power supply associated with the first clock signal. The first integrated level shifter and latch circuitry receives an input signal in a first power supply domain, and latches a value the input signal based on the second clock signal. Further, the first integrated level shifter and latch circuitry outputs, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.

First claim

What is claimed is:

1. A memory device comprising:
clock signal generation circuitry configured to receive a first clock signal and an isolation signal, and generate a second clock signal based on the first clock signal and the isolation signal, the isolation signal corresponds to a power state of a power supply associated with the first clock signal, wherein the second clock signal maintains a first voltage value based on the isolation signal indicating a power off state of the power supply and that the first clock signal is stopped, and the second clock signal includes transitions between the first voltage value and a second voltage value based on the isolation signal indicating a power on state of the power supply; and
first integrated level shifter and latch circuitry configured to:
receive an input signal in a first power supply domain;
latch a value the input signal based on the second clock signal, wherein the first integrated level shifter maintains the latch of the value based on the second clock signal maintaining the first voltage value and the isolation signal indicating the power off state of the power supply and that the first clock signal is stopped; and
output, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.

2. The memory device of claim 1 , wherein generating the second clock signal includes maintaining a voltage level of the second clock signal at the first voltage value based on the isolation signal indicating the power off state of the power supply.

3. The memory device of claim 1 , wherein the clock signal generation circuitry comprises:
level shifter circuitry configured to receive the first clock signal in the first power supply domain and output a shifted clock signal in a second power domain; and
combinatorial logic configured to receive the shifted clock signal and the isolation signal, and generate the second clock signal based on the shifted clock signal and the isolation signal.

4. The memory device of claim 1 , wherein the first integrated level shifter and latch circuitry comprises:
first transistors configured to shift the input signal from the first power supply domain to the second power supply domain based on the second clock signal having a first value;
second transistors coupled to the first transistors and configured to latch a value based on the second clock signal having a second value; and
third transistors configured to output a first output signal based on a clamping signal, wherein the output signal corresponds to one of the shifted input signal and the latched value.

5. The memory device of claim 4 , wherein the first transistors comprise cross-coupled PMOS transistors.

6. The memory device of claim 4 , wherein the second transistors comprise cross-coupled NMOS transistors.

7. The memory device of claim 4 , wherein the third transistors are configured to disconnect one or more of the second transistors from a reference voltage based on the clamping signal.

8. The memory device of claim 1 further comprising:
decode circuitry configured to receive the output signal from the first integrated level shifter and latch circuitry and output one or more control signals, wherein the input signal includes address data for a memory command; and
bitcell array configured to receive the one or more control signals, wherein the one or more control signals are configured to active a row and column within the bitcell array.

9. The memory device of claim 8 further comprising:
sense amplifier circuitry coupled to the bitcell array, and configured to output a first data signal from the bitcell array;
write driver circuitry coupled to the bitcell array and configured to write a second data signal to the bitcell array;
second integrated level shifter and latch circuitry connected to an output of the sense amplifier circuitry, and configured to receive the first data signal and shift the first data signal from the second power supply domain to the first power supply domain; and
third integrated level shifter and latch circuitry coupled to an input of the sense amplifier circuitry, and configured to receive the second data signal and shift the second data signal from the first power supply domain to the second power supply domain, wherein the driver circuitry is configured to receive the second data signal in the second power supply domain.

10. The memory device of claim 1 further comprising:
testing circuitry comprising:
a first functional path comprising the first integrated level shifter and latch circuitry, wherein the input signal is a first data signal; and
scan chain circuitry coupled to the output of the first integrated level shifter and latch circuitry and to an output of level shifter circuitry, the scan chain circuitry configured to output a second output signal based on one of the output of the first integrated level shifter and latch circuitry and the output of level shifter circuitry.

11. A circuit device configured to:
receive a first input signal in a first power supply domain;
latch a value of the first input signal based on a latch clock signal, wherein the latch clock signal is generated based on a first clock signal associated with the first power supply domain and an isolation signal that corresponds to a power state of a power supply associated with the first power supply domain, wherein the latch clock signal maintains a first voltage value based on the isolation signal indicating a power off state of the power supply and that the first clock signal is stopped, and the latch clock signal includes transitions between the first voltage value and a second voltage value based on the isolation signal indicating a power on state of the power supply;
maintain the latch of the value based on the latch clock signal maintaining the first voltage value and the isolation signal indicating the power off state of the power supply and that the first clock signal is stopped; and
output, based on the latched value, a first output signal in a second power supply domain different than the first power supply domain.

12. The circuit device of claim 11 further comprising:
first transistors configured to shift the first input signal from the first power supply domain to the second power supply domain based on the latch clock signal having a first value;
second transistors coupled to the first transistors and configured to latch a value of the first input signal based on the latch clock signal having a second value; and
third transistors configured to output the first output signal based on a clamping signal, wherein the first output signal corresponds to one of the shifted input signal and the latched value.

13. The circuit device of claim 12 , wherein the first transistors comprise first cross-coupled transistors, and wherein the second transistors comprise second cross-coupled transistors.

14. The circuit device of claim 12 , wherein the third transistors are configured to disconnect one or more of the second transistors from a reference voltage based on the clamping signal.

15. An integrated circuit (IC) device comprising:
logic circuitry configured to output a first clock signal and a control signal, wherein the logic circuitry operates in a first power supply domain;
memory circuitry configured to receive the first clock signal and one or more data signals, the memory circuitry comprising:
clock signal generation circuitry configured to receive the first clock signal and an isolation signal, and generate a second clock signal based the first clock signal and the isolation signal,

Assignees

• Synopsys Inc

Inventors

• Pilo Harold
• Kumar Shishir
• Garg Anurag
• Lee Peter
• Barth John Edward

Classifications

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• G11C29/10

  Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns · CPC title

• G11C8/10

  Decoders · CPC title