Method and apparatus for memory noise-free wake-up protocol from power-down

Patent metadata

Field	Value
Publication number	US-10971218-B2
Application number	US-201916423554-A
Country	US
Kind code	B2
Filing date	May 28, 2019
Priority date	May 28, 2019
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

A memory device having a wake-up protocol is disclosed. The memory device comprises a plurality of bitcells operative in a deep-sleep mode having corresponding bitline pairs coupled to the plurality of bitcells, a first PFET coupled between a core voltage supply and the plurality of bitcells configured to supply a core voltage to the plurality of bitcells, and a second PFET having a drain coupled to the plurality of bitcells, a source coupled to a gate of the first PFET, and a gate configured to receive a first wake signal to enable precharge of the plurality of bitcells.

First claim

I claim:

1. A memory device having a wake-up protocol comprising:
a plurality of bitcells having corresponding bitline pairs coupled to the plurality of bitcells;
a first transistor coupled between a voltage core supply and the plurality of bitcells configured to supply a core voltage to the plurality of bitcells, the first transistor configured to receive a second wake signal to charge the plurality of bitcells to the core voltage; and
a second transistor having a drain coupled to the plurality of bitcells, a source coupled to a gate of the first transistor, and a gate configured to receive a first wake signal to enable precharge of the plurality of bitcells, wherein a delay is introduced between application of the first wake signal and the second wake signal.

2. The memory device of claim 1 , further comprising:
a delay circuit for introducing the delay between the application of the first wake signal and the second wake signal.

3. The memory device of claim 1 , wherein the first wake signal turns on the second transistor.

4. The memory device of claim 3 , wherein the first transistor is configured as a diode coupled between the gate of the first transistor and a drain of the first transistor.

5. The memory device of claim 1 , wherein the first transistor precharges the plurality of bitcells to a transitional core voltage.

6. A memory device comprising:
a plurality of bitline cross-coupled transistors operative in a deep-sleep mode having corresponding bitline pairs with each pair coupled to a respective bitline cross-coupled transistors;
a plurality of corresponding bitline precharge transistors coupled to an input voltage supply and to the corresponding bitline pairs of the plurality of bitline cross-coupled transistors;
a first transistor coupled between the input voltage supply and the plurality of bitline cross-coupled transistors configured to precharge the bitline pairs to a first voltage level in response to a wake signal wherein the plurality of bitline precharge transistors charges the bitline pairs to a second voltage level in response to a bitline restore signal; and
a delay circuit coupled between the first transistor and the plurality of corresponding bitline precharge transistors, the delay circuit for introducing a delay to the wake signal to generate the bitline restore signal.

7. The memory device of claim 6 , wherein the first voltage level is a transitional voltage level of the second voltage level.

8. A method of operating a memory device, said memory device having a plurality of bitcells with corresponding bitline pairs, the method comprising:
applying a second wake signal to a first transistor coupled between a voltage core supply and the plurality of bitcells, the first transistor for supplying a core voltage to the plurality of bitcells, the second wake signal for charging the plurality of bitcells to the core voltage, and
applying a first wake signal to a gate of a second transistor having a drain coupled to the plurality of bitcells and a source coupled to a gate of the first transistor, the first wake signal for precharging the plurality of bitcells from the deep-sleep mode, wherein a delay is introduced between application of the first wake signal and the second wake signal.

9. The method of operating a memory device of claim 8 , further comprising the step of introducing a predetermined time delay between applying the first wake signal and the second wake signal.

10. The method of operating a memory device of claim 8 , wherein the step of turning on the second transistor includes the step of limiting the first transistor to charge the plurality of bitcells to a transitional voltage.

11. The method of operating a memory device of claim 10 , wherein the step of applying the first wake signal to a gate of the second transistor to precharge the plurality of bitcells includes the step of clamping the gate and the drain of the first transistor to a diode drop to precharge the plurality of bitcells.

12. The method of operating a memory device of claim 8 , wherein the step of applying the second wake signal includes the step of turning off the first wake signal.

13. The method of operating a memory device of claim 12 , wherein the step of turning off the first wake signal includes the step of turning off the second transistor.

14. A method of operating a memory device, comprising:
applying a wake signal to a first transistor coupled between an input voltage supply and a plurality of bitline cross-coupled transistors, the plurality of bitline cross-coupled transistors having corresponding bitline pairs having each pairs;
applying a bitline restore signal to a plurality of corresponding bitline precharge transistors coupled to the input voltage supply, the plurality of corresponding bitline precharge transistors having corresponding bitline pairs coupled to the plurality of bitline cross-coupled transistors; and
introducing a delay to the wake signal to generate the bitline restore signal.

15. The method of operating a memory device of claim 14 , wherein the step of applying the wake signal includes the step of pre-charging the first voltage level to a transitional voltage.

16. The method of operating a memory device of claim 14 , wherein the step of applying the bitine restore signal includes the step of maintaining the wake signal to the first transistor.

Assignees

• Synopsys Inc

Inventors

• Pilo Harold

Classifications

• G11C2207/2227

  Standby or low power modes · CPC title

• G11C11/417 Primary

  for memory cells of the field-effect type · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title