Scan chain compression for testing memory of a system on a chip

Patent metadata

Field	Value
Publication number	US-12112818-B2
Application number	US-202217856744-A
Country	US
Kind code	B2
Filing date	Jul 1, 2022
Priority date	Jul 5, 2021
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one, and in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.

First claim

What is claimed is:

1. A method of using on-chip circuitry to test a memory of a chip, the method comprising:
in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory of the chip, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one;
in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, and providing the single compressed address value to a second stage latch of the first n-bit compression structure; and
in a testing stage, comparing the single compressed address value of the second stage latch of the first n-bit compression structure, as output from the first n-bit compression structure, to a desired value to determine whether an interface to the memory is operating as desired.

2. The method of claim 1 , wherein n has a value of four.

3. The method of claim 2 , further comprising:
in the capture stage for capturing a value of a particular latch of the four first stage latches, setting values of the remaining three latches of the four first stage latches to 0, such that an output of a NAND gate of the four-bit compression structure, which is the single compressed address value, matches the value of the particular latch, the particular latch being connected to a particular memory address of the memory; and
in the testing stage for testing an interface to the particular memory address of the memory, comparing the value of the second stage latch of the four-bit compression structure, as output from the four-bit compression structure, to a known correct value of the particular memory address to determine whether the interface to the particular memory address is operating as desired.

4. The method of claim 2 , further comprising:
in the capture stage, passing the single compressed address value from a first multiplexer to the second stage latch;
switching from the capture stage to a scan stage based on another input into the first multiplexer; and
after switching from the capture stage to the scan stage passing a value received on the other input into the first multiplexer to the second stage latch.

5. The method of claim 4 , further comprising, after switching from the capture stage to the scan stage, passing the previously stored single compressed address value from the second stage latch to a latch of a second four-bit compression structure.

6. The method of claim 4 , further comprising switching from the capture stage to the scan stage in dependence upon a scan enable (SE) signal of the chip.

7. The method of claim 2 , further comprising:
in the capture stage for capturing a value of a particular latch of the four first stage latches, setting values of the remaining three latches of the four first stage latches to 1, such that an output of a NOR gate of the four-bit compression structure, which is the single compressed address value, matches the value of the particular latch, the particular latch being connected to a particular memory address of the memory; and
in the testing stage for testing an interface to the particular memory address of the memory, comparing the value of the second stage latch of the four-bit compression structure, as output from the four-bit compression structure, to a known correct value of the particular memory address to determine whether the interface to the particular memory address is operating as desired.

8. The method of claim 1 , further comprising:
in a scan stage, passing the value of the second stage latch of the first n-bit compression structure to a latch of a second n-bit compression structure; and
in the capture stage, receiving, at the second n-bit compression structure including n first stage latches corresponding to each bit of the second n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch, of the second n-bit compression structure, receives a respective value from a memory address of the memory, n being an integer greater than one.

9. The method of claim 8 , further comprising, in the testing stage, comparing the value of the second stage latch of the second n-bit compression structure, as output from the second n-bit compression structure, to a desired value to determine whether the memory is operating as desired.

10. A system for testing a memory of a chip, the system comprising:
a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, the first n-bit compression structure being configured to receive, in a capture stage, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one,
wherein the first n-bit compression structure further includes compression logic and a second stage latch, such that, in the capture stage, the values are passed from each respective first stage latch through the compression logic to output a single compressed address value and the single compressed address value is provided to the second stage latch.

11. The system of claim 10 , further comprising testing logic configured to, in a testing stage, compare the value of the second stage latch of the first n-bit compression structure, as output from the first n-bit compression structure, to a value to determine whether an interface to the memory is operating as desired.

12. The system of claim 11 , wherein n has a value of four.

13. The system of claim 12 ,
wherein the four-bit compression structure includes:
a first NOR gate connected to outputs of a first two of the four first stage latches and configured to, in the capture stage, receive values from a first two of four first stage latches as inputs;
a second NOR gate connected to outputs of a second two of the four first stage latches and configured to, in the capture stage, receive values from a second two of the four first stage latches as inputs;
a NAND gate having inputs connected to outputs of the first and second NOR gates and configured to, in the capture stage, receive an output of the first and second NOR gates as the single compressed value; and
a first multiplexer connected to an output of the NAND gate and configured to receive the output of the NAND gate.

14. The system of claim 12 ,
wherein the four-bit compression structure includes:
a first NAND gate connected to outputs of a first two of four first stage latches and configured to, in the capture stage, receive values from the first two of the four first stage latches as inputs;
a second NAND gate connected to outputs of a second two of the four first stage latches and configured to, in the capture stage, receive values from the second two of the four first stage latches as inputs;
a NOR gate having inputs connected to outputs of the first and second NAND gates and configured to, in the capture stage, receive values output from the first and second NAND gates as the single compressed address value; and
a first multiplexer connected to an output of the NOR gate and configured to receive the single compressed address value output from the NOR gate.

15. The system of claim 1

Assignees

• Synopsys Inc

Inventors

• Pilo Harold
• Kumar Shishir

Classifications

• G11C29/30

  Accessing single arrays · CPC title

• G11C2029/3202

  Scan chain · CPC title

• G11C29/32

  Serial access; Scan testing · CPC title

• G11C29/40 Primary

  using compression techniques · CPC title