Reduced circuit area memory device with a half-word memory architecture

Patent metadata

Field	Value
Publication number	US-12340865-B2
Application number	US-202318143560-A
Country	US
Kind code	B2
Filing date	May 4, 2023
Priority date	May 4, 2023
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

A memory device includes a memory device and control circuitry. The memory array includes bitcells and bitlines connected to the bitcells. The bitcells are grouped into bitcell groups. The control circuitry is connected to the bitcell groups via the bitlines. The control circuitry adjusts connections with the bitcell groups to include a first bitcell group of the bitcell groups in memory operations and exclude a second bitcell group of the bitcell groups from the memory operations based on a half-word control signal being enabled.

First claim

What is claimed is:

1. A memory device comprising:
a memory array comprising bitcells and bitlines connected to the bitcells, wherein the bitcells are grouped into bitcell groups; and
a control circuitry connected to the bitcell groups via the bitlines, and configured to, based on a half-word control signal being enabled, adjust connections with the bitcell groups to include a first bitcell group of the bitcell groups in memory operations and exclude a second bitcell group of the bitcell groups from the memory operations.

2. The memory device of claim 1 , wherein the control circuitry comprises:
a write driver circuitry comprising write drivers connected to the bitlines;
a shift control circuitry comprising first shift circuits connected to the write drivers, wherein each of the first shift circuits is configured to output write signals to two of the write drivers; and
an input/output circuitry comprising input/output circuits, each input/output circuit is connected to a respective one of the first shift circuits, and wherein the output of each input/output circuit is gated based on the half-word control signal.

3. The memory device of claim 2 , wherein the input/output circuits are configured to output write signals based on the half-word control signal being enabled and a data signal.

4. The memory device of claim 2 , wherein the first shift circuits are interconnected and configured to output shift control signals between the first shift circuits, wherein the shift control signals indicate which write driver of the write drivers to output write signals.

5. The memory device of claim 2 , wherein the control circuitry further comprises a decoder circuitry connected to the first shift circuits and configured to output a control signal to each of the first shift circuits that provides an indication to one of the first shift circuits to shift outputting write signals from a first write driver of the write drivers to a second write driver of the write drivers.

6. The memory device of claim 2 , wherein the control circuitry further comprises:
a sense amplifier circuitry comprising sense amplifiers, each of the sense amplifiers is coupled to the bitlines, and configured to receive data from the bitlines, wherein the shift control circuitry includes second shift circuits coupled to the sense amplifiers, and wherein outputting data signals from the sense amplifiers to the second shift circuits is gated based on the half-word control signal.

7. The memory device of claim 6 , wherein the sense amplifier circuitry further comprises a selection circuit, the selection circuit is configured to output a first bit of the half-word control signal or a second bit of the half-word control signal to a first sense amplifier of the sense amplifiers based on a shift control signal output from a second sense amplifier of the sense amplifiers.

8. The memory device of claim 6 , wherein the control circuitry further comprises a decoder circuitry connected to the second shift circuits and configured to output a control signal to each of the second shift circuits that provides an indication to one of the second shift circuits to shift receiving data signals from a first sense amplifier of the sense amplifiers to a second sense amplifier of the sense amplifiers.

9. The memory device of claim 6 , wherein the second shift circuits are interconnected and configured to output shift control signals between the second shift circuits, wherein the shift control signals indicate which sense amplifier of the sense amplifiers to receive data signals.

10. The memory device of claim 6 , wherein each of the sense amplifiers is configured to output a data signal based on the half-word control signal and a sense amplifier enable signal.

11. A control circuitry comprising:
a shift control circuitry configured to, based on a half-word control signal being enabled, adjust connections between the control circuitry and bitcells groups of a memory array to include a first bitcell group of the bitcell groups in memory operations and exclude a second bitcell group of the bitcell groups from the memory operations, wherein the memory array comprises bitlines connected to bitcells of the bitcells groups.

12. The control circuitry of claim 11 further comprising:
a write driver circuitry comprising write drivers connected to the bitlines; and
an input/output circuitry comprising input/output circuits, each input/output circuit is connected to a respective one of first shift circuits of the shift control circuitry, wherein the output of each input/output circuit is gated based on the half-word control signal, and wherein the first shift circuits are connected to the write drivers, and wherein each of the first shift circuits is configured to output write signals to two of the write drivers.

13. The control circuitry of claim 12 , wherein a the input/output circuits are configured to output write signals based on the half-word control signal being enabled and a data signal.

14. The control circuitry of claim 12 , wherein the first shift circuits are interconnected and configured to output shift control signals between the first shift circuits, wherein the shift control signals indicate which write driver of the write drivers to output write signals.

15. The control circuitry of claim 12 , wherein the control circuitry further comprises a decoder circuitry connected to the first shift circuits and configured to output a control signal to each of the first shift circuits that provides an indication to one of the first shift circuits to shift outputting write signals from a first write driver of the write drivers to a second write driver of the write drivers.

16. The control circuitry of claim 12 , wherein the control circuitry further comprises:
a sense amplifier circuitry comprising sense amplifiers, each of the sense amplifiers is coupled to the bitlines, and configured to receive data from the bitlines, wherein the shift control circuitry includes second shift circuits coupled to the sense amplifiers, and wherein outputting data signals from the sense amplifiers to the second shift circuits is gated based on the half-word control signal.

17. The control circuitry of claim 16 , wherein the sense amplifier circuitry further comprises a selection circuit, the selection circuit is configured to output a first bit of the half-word control signal or a second bit of the half-word control signal to a first sense amplifier of the sense amplifiers based on a shift control signal output from a second sense amplifier of the sense amplifiers.

18. The control circuitry of claim 16 , further comprising a decoder circuitry connected to the second shift circuits and configured to output a control signal to each of the second shift circuits that provides an indication to one of the second shift circuits to shift receiving data signals from a first sense amplifier of the sense amplifiers to a second sense amplifier of the sense amplifiers.

19. The control circuitry of claim 16 , wherein each of the sense amplifiers is configured to output a data signal based on the half-word control signal and a sense amplifier enable signal.

20. A memory device comprising:
a memory array comprising bitcells and bitlines connected to the bitcells;
a control circuitry connected the memory array and comprising:
a write driver circuitry comprising write drivers connected to the bitlines;
a sense amplifier circuitry comprising sense amplifiers, each of the sense amplifiers is coupled to the bitlines, and confi

Assignees

• Synopsys Inc

Inventors

• Pilo Harold
• Behera Niranjan

Classifications

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G11C7/08 Primary

  Control thereof · CPC title

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• G11C29/848

  by adjacent switching · CPC title

• G11C29/808

  using a flexible replacement scheme · CPC title