Power supply tracking circuitry for embedded memories

Patent metadata

Field	Value
Publication number	US-12094513-B2
Application number	US-202217966680-A
Country	US
Kind code	B2
Filing date	Oct 14, 2022
Priority date	Oct 27, 2021
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

Tracking circuitry for a memory device is disclosed. The tracking circuitry includes an inverter, a level shifter, delay circuitry, and a logic gate. The inverter is configured to receive a first clock signal and generate an inverted clock signal. The level shifter is configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal. The delay circuitry is configured to receive the level shifted clock signal and generate an inverted level shifted clock signal. The logic gate comprises a first input configured to receive the first clock signal and a second input configured to receive the inverted level shifted clock signal. The logic gate is configured to generate a second clock signal based on the first clock signal and the inverted level shifted clock signal.

First claim

What is claimed is:

1. A tracking circuitry comprising:
an inverter configured to receive a first clock signal and generate an inverted clock signal in a first power supply voltage domain;
a level shifter configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal in a second power supply voltage domain different from the first power supply voltage domain;
delay circuitry configured to receive the level shifted clock signal and generate an inverted level shifted clock signal; and
a logic gate comprising a first input configured to receive the first clock signal and a second input configured to receive the inverted level shifted clock signal, wherein the logic gate is configured to generate a second clock signal based on the first clock signal and the inverted level shifted clock signal.

2. The tracking circuitry of claim 1 , wherein the logic gate is a NOR gate.

3. The tracking circuitry of claim 1 , wherein a rising edge of the second clock signal corresponds to the first power supply voltage domain and a falling edge of the second clock signal corresponds to the second power supply voltage domain.

4. The tracking circuitry of claim 1 , wherein the logic gate comprises a first transistor having a gate coupled to the first input and a second transistor having a gate coupled to the second input and a source coupled to a drain of the first transistor, wherein the first transistor blocks current flow from the second transistor when a voltage value of the first input is a low voltage level.

5. The tracking circuitry of claim 1 , wherein the inverted clock signal is used by a data latch to generate a bitline input to a bitcell of a memory device.

6. The tracking circuitry of claim 1 , wherein the inverted clock signal is used by a bitline precharge latch to precharge a bitline input path to a bitcell.

7. The tracking circuitry of claim 1 , wherein the inverted clock signal is used by an address signal latch to generate a wordline input to a bitcell of a memory device.

8. The tracking circuitry of claim 1 , wherein the delay circuitry comprises an odd number of inverters.

9. A memory device comprising:
bitcells configured to operate in a first power supply voltage domain;
a memory core circuitry coupled to the bitcells and configured to generate a control signal in the first power supply voltage domain to write data to the bitcells; and
a control circuitry coupled to the memory core circuitry, the control circuitry configured to generate a data clock signal in a second power supply voltage domain different than the first power supply voltage domain, wherein a rising edge of the data clock signal corresponds to the second power supply voltage domain and a falling edge of the data clock signal correspond to the first power supply voltage domain.

10. The memory device of claim 9 , wherein the data clock signal generated by the control circuitry is used by the memory core circuitry to generate a bitline input to the bitcells.

11. The memory device of claim 9 , wherein a wordline input to the bitcells operates in the first power supply voltage domain and a bitline input to the bitcells operates in the second power supply voltage domain.

12. The memory device of claim 9 , wherein the first power supply voltage domain is higher than the second power supply voltage domain.

13. The memory device of claim 9 , wherein the first power supply voltage domain is lower than the second power supply voltage domain.

14. The memory device of claim 9 , wherein the control circuitry is further configured to generate an address clock signal in the second power supply voltage domain.

15. The memory device of claim 9 , wherein the control circuitry generates the data clock signal in the second power supply voltage domain via a tracking circuitry in a buffer of the control circuitry.

16. A memory device comprising:
bitcells configured to operate in a first power supply voltage domain;
a memory core circuitry coupled to the bitcells and configured to generate a control signal in the first power supply voltage domain to write data to the bitcells; and
a control circuitry coupled to the memory core circuitry, the control circuitry configured to generate an address clock signal in a second power supply voltage domain different than the first power supply voltage domain, wherein a rising edge of the address clock signal corresponds to the second power supply voltage domain and a falling edge of the address clock signal correspond to the first power supply voltage domain.

17. The memory device of claim 16 , wherein the address clock signal generated by the control circuitry is used by the memory core circuitry to generate a wordline input to the bitcells.

18. The memory device of claim 16 , wherein a wordline input to the bitcells operates in the first power supply voltage domain and a bitline input to the bitcells operates in the second power supply voltage domain.

19. The memory device of claim 16 , wherein the control circuitry generates the address clock signal in the second power supply voltage domain via a tracking circuitry in a buffer of the control circuitry.

20. The memory device of claim 16 , wherein the first power supply voltage domain is less than the second power supply voltage domain.

Assignees

• Synopsys Inc

Inventors

• Pilo Harold
• Kumar Shishir
• Garg Anurag

Classifications

• G11C11/2259

  Cell access · CPC title

• G11C11/2255

  Bit-line or column circuits · CPC title

• G11C2207/229

  Timing of a write operation · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title