Method of manufacturing semiconductor chips having a side wall sealing
US-12525499-B2 · Jan 13, 2026 · US
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Muri Ingo patents
Muri Ingo is listed as an inventor on 82 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Muri Ingo |
| Total patents | 82 |
| First publication | Mar 5, 2015 |
| Latest publication | Jan 13, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Transistor device and method of manufacturing
US-2025366146-A1 · Nov 27, 2025 · US
Method for producing a superjunction device
US-12484242-B2 · Nov 25, 2025 · US
Transistor device and method of manufacturing
US-12419096-B2 · Sep 16, 2025 · US
Semiconductor wafer including a test structure
US-2025112097-A1 · Apr 3, 2025 · US
Power relay circuit
US-12176172-B2 · Dec 24, 2024 · US
Semiconductor device having semiconductor device elements in a semiconductor layer
US-12107130-B2 · Oct 1, 2024 · US
Superjunction transistor device
US-2024321953-A1 · Sep 26, 2024 · US
Superjunction transistor device and method for forming a superjunction transistor device
US-12034040-B2 · Jul 9, 2024 · US
Method for producing a superjunction device
US-2024128356-A1 · Apr 18, 2024 · US
Recent patents
Latest publications not already listed above.
Superjunction transistor device
US-11929395-B2 · Mar 12, 2024 · US
Method for producing a superjunction device
US-11894445-B2 · Feb 6, 2024 · US
Method of porosifying part of a semiconductor wafer
US-11810779-B2 · Nov 7, 2023 · US
Method for producing a superjunction device
US-11652138-B2 · May 16, 2023 · US
Semiconductor device including an electrical contact with a metal layer arranged thereon
US-11552048-B2 · Jan 10, 2023 · US
Method of Manufacturing Semiconductor Chips having a Side Wall Sealing
US-2022352048-A1 · Nov 3, 2022 · US
Method of porosifying part of a semiconductor wafer
US-2022310380-A1 · Sep 29, 2022 · US
Superjunction Transistor Device
US-2022270933-A1 · Aug 25, 2022 · US
Transistor device and method of manufacturing
US-2022246744-A1 · Aug 4, 2022 · US
Method for partially removing a semiconductor wafer
US-11404262-B2 · Aug 2, 2022 · US
Method for forming a superjunction transistor device
US-11348838-B2 · May 31, 2022 · US
Semiconductor chip including back-side conductive layer
US-11328955-B2 · May 10, 2022 · US
Superjunction transistor device
US-2022052154-A1 · Feb 17, 2022 · US
Method for Producing a Superjunction Device
US-2022052182-A1 · Feb 17, 2022 · US
Power Relay Circuit
US-2021407746-A1 · Dec 30, 2021 · US
Semiconductor device manufacturing by thinning and dicing
US-2021391218-A1 · Dec 16, 2021 · US
Method of thinning a semiconductor substrate to high evenness and semiconductor substrate having a device layer of high evenness
US-2021391377-A1 · Dec 16, 2021 · US
Superjunction transistor device and method for forming a superjunction transistor device
US-2021376063-A1 · Dec 2, 2021 · US
Method for producing a superjunction device
US-2021376064-A1 · Dec 2, 2021 · US
Method for forming a superjunction transistor device
US-11189690-B2 · Nov 30, 2021 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Infineon Technologies Ag | 60 |
| Infineon Technologies Austria Ag | 23 |
| Infineon Techologies Ag | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D30/66 | 26 |
| H10D62/111 | 22 |
| H10P52/00 | 20 |
| H10D30/0291 | 18 |
| H10D62/8325 | 18 |