Superjunction transistor device and method for forming a superjunction transistor device

Patent metadata

Field	Value
Publication number	US-12034040-B2
Application number	US-202117330562-A
Country	US
Kind code	B2
Filing date	May 26, 2021
Priority date	May 27, 2020
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

A method for forming a drift region of a superjunction transistor and a superjunction transistor device are disclosed. The method includes forming first regions of a first doping type and second regions of a second type in a semiconductor body such that the first and second regions are arranged alternatingly in the body. The first and second regions are formed by: forming trenches in at least one semiconductor layer; implanting first type dopant atoms and second type dopant atoms into opposing sidewalls of the trenches; filling the trenches with a semiconductor material; and diffusing the dopant atoms in a thermal process so that the first type dopant atoms form the first regions and the second type dopant atoms form the second regions. Each trench has a first width, the trenches are separated by mesa regions each having a second width, and the first width is greater than the second width.

First claim

What is claimed is:

1. A method, comprising:
forming a plurality of first regions of a first doping type and a plurality of second regions of a second type in a semiconductor body such that the first regions and the second regions are arranged alternatingly in the semiconductor body,
wherein forming the first regions and the second regions comprises:
forming a plurality of trenches in at least one semiconductor layer;
implanting first type dopant atoms and second type dopant atoms into each of opposing sidewalls of the plurality of trenches;
filling the plurality of trenches with a semiconductor material; and
diffusing the first type dopant atoms and the second type dopant atoms in a thermal process so that the first type dopant atoms form the first regions and the second type dopant atoms form the second regions,
wherein each of the plurality of trenches has a first width,
wherein the trenches are separated by mesa regions each having a second width,
wherein the first width is greater than the second width,
wherein the second type dopant atoms are implanted deeper into the sidewalls than the first type dopant atoms, and
wherein the second type dopant atoms are faster diffusing than the first type dopant atoms.

2. The method of claim 1 , wherein the first width is at least 1.05 times the second width.

3. The method of claim 1 , wherein the first width is less than 3 times the second width.

4. The method of claim 1 , wherein an aspect ratio of the trenches is between 2:1 and 3:1.

5. The method of claim 1 , wherein the first type dopant atoms comprise at least one of arsenic and antimony atoms, and wherein the second type dopant atoms comprise boron atoms.

6. The method of claim 1 , wherein an overall amount of the first type dopants implanted into each of the sidewalls deviates less than 5% from an overall amount of the second type dopant atoms implanted into the respective sidewall.

7. The method of claim 1 , wherein filling the trenches comprises forming an epitaxial layer in the trenches and on top of the mesa regions.

8. The method of claim 1 , wherein forming the plurality of trenches in the at least one semiconductor layer comprises:
forming a plurality of semiconductor layers one above the other; and
forming a plurality of trenches in each of the plurality of semiconductor layers before forming a next one of the plurality of semiconductor layers.

9. The method of claim 1 , further comprising:
forming a control structure with a plurality of source regions of the first doping type and a plurality of body regions of the second doping type such that each of the first regions adjoins at least one of the plurality of body regions and each of the second regions adjoins at least one of the plurality of body regions.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Weber Hans
• Muri Ingo
• Tutuc Daniel

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P32/12

  between a solid phase and a gaseous phase · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title