Method for producing a superjunction device

Patent metadata

Field	Value
Publication number	US-11894445-B2
Application number	US-202117393779-A
Country	US
Kind code	B2
Filing date	Aug 4, 2021
Priority date	Aug 11, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.

First claim

What is claimed is:

1. A method, comprising:
forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements comprises:
forming a semiconductor layer;
forming a plurality of trenches in a first surface of the semiconductor layer; and
implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches, and wherein forming of at least one of the plurality of semiconductor arrangements further comprises:
forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer,
wherein the plurality of semiconductor arrangements comprises at least four semiconductor arrangements, and wherein forming of at least one but not all of the semiconductor arrangements comprises forming the protective layer.

2. The method of claim 1 , wherein the protective layer has a thickness of between 25 nm and 200 nm, between 50 nm and 200 nm, or between 100 nm and 200 nm.

3. The method of claim 1 , wherein forming the protective layer comprises epitaxially growing the protective layer at a temperature of between 650° C. and 1000° C., or between 800° C. and 950° C.

4. The method of claim 1 , wherein forming the semiconductor layer comprises epitaxially growing the semiconductor layer at a temperature of 1000° C. or more, or at a temperature of 1100° C. or more.

5. The method of claim 1 , wherein the plurality of semiconductor arrangements comprises at least one pair of semiconductor arrangements with a bottom semiconductor arrangement and a top semiconductor arrangement adjoining the bottom semiconductor arrangement, and wherein forming the semiconductor layer of the top semiconductor arrangement comprises forming the semiconductor layer in the plurality of trenches and on top of mesa regions between the plurality of trenches of the semiconductor layer of the bottom semiconductor arrangement.

6. The method of claim 5 , wherein forming the bottom semiconductor arrangement comprises forming a protective layer, and wherein forming the semiconductor layer of the top semiconductor arrangement comprises forming the semiconductor layer such that the protective layer is arranged between the bottom semiconductor arrangement and the semiconductor layer of the top semiconductor arrangement.

7. The method of claim 5 , further comprising:
performing a pre-conditioning step after forming the bottom semiconductor arrangement and before forming the top semiconductor arrangement, wherein the pre-conditioning step comprises removing contaminants, native oxide, or chemically formed oxide formed on the bottom semiconductor arrangement.

8. The method of claim 7 , wherein removing contaminants, native oxide, or chemically formed oxide formed on the bottom semiconductor arrangement comprises performing an etching or removal step in a plasma chamber.

9. The method of claim 7 , wherein the pre-conditioning step is performed at a temperature of between 15° C. and 600° C.

10. The method of claim 8 , wherein forming the protective layer comprises forming the protective layer in an epitaxy chamber directly adjoining the plasma chamber such that the pre-conditioned bottom semiconductor arrangement does not come into contact with oxygen between the pre-conditioning step and forming the protective layer.

11. The method of claim 1 , wherein each of the plurality of trenches is arranged in one of at least two sections, and wherein when forming a semiconductor arrangement without a protective layer, an implantation dose of at least one of the first type dopant atoms and the second type dopant atoms for each of the at least two sections differs from the implantation dose of the corresponding type of dopant atoms of at least one other section of the at least two sections.

12. The method of claim 1 , wherein implanting the dopant atoms comprises:
implanting dopant atoms of the first type into the first sidewall; and
implanting dopant atoms of the second type into the second sidewall.

13. The method of claim 1 , wherein implanting the dopant atoms comprises:
implanting dopant atoms of both the first type and the second type into at least one of the first sidewall and the second sidewall.

14. The method of claim 1 , further comprising:
annealing the semiconductor body to diffuse the dopant atoms.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Tutuc Daniel
• Kuenle Matthias
• Muri Ingo
• Weber Hans

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10D62/058

  by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D30/66 Primary

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title