Semiconductor device manufacturing by thinning and dicing

Patent metadata

Field	Value
Publication number	US-2021391218-A1
Application number	US-202117343885-A
Country	US
Kind code	A1
Filing date	Jun 10, 2021
Priority date	Jun 15, 2020
Publication date	Dec 16, 2021
Grant date	—

Abstract

A method of manufacturing a semiconductor device is described. A semiconductor substrate is provided. The semiconductor substrate includes a semiconductor substrate layer and a semiconductor device layer. The method includes transforming areas of the semiconductor device layer into dicing areas which can be removed by etching, and removing the semiconductor substrate layer and the dicing areas by using etching.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate comprising a semiconductor substrate layer and a semiconductor device layer; transforming areas of the semiconductor device layer into dicing areas which can be removed by etching; and removing the semiconductor substrate layer and the dicing areas by using etching.

2 . The method of claim 1 , wherein the transforming comprises:
depositing a dopant into the dicing areas.

3 . The method of claim 2 , wherein depositing the dopant into the dicing areas comprises:
depositing the dopant into the dicing areas by dopant implantation.

4 . The method of claim 2 , wherein depositing the dopant into the dicing areas comprises:
depositing the dopant into the dicing areas by dopant diffusion.

5 . The method of claim 4 , wherein depositing the dopant into the dicing areas by dopant diffusion comprises:
generating one or more trenches in each of the dicing areas; filling the one or more trenches of a dicing area with a high-doped filler material; and allowing the dopant in the high-doped filler material to diffuse out into the dicing area.

6 . The method of claim 4 , wherein depositing the dopant into the dicing areas by dopant diffusion comprises:
forming a high-doped dopant donator structure atop each of the dicing areas; and allowing the dopant in the high-doped dopant donator structure to diffuse out into the dicing area.

7 . The method of claim 1 , wherein the semiconductor substrate layer is a high-doped layer.

8 . The method of claim 1 , wherein the etching is dopant-selective chemical etching.

9 . The method of claim 1 , wherein the semiconductor substrate further comprises a semiconductor etch stop layer arranged between the semiconductor substrate layer and the semiconductor device layer.

10 . The method of claim 9 , further comprising:
transforming areas of the semiconductor etch stop layer to form part of the dicing areas which can be removed by etching.

11 . The method of claim 9 , wherein the semiconductor etch stop layer is a low-doped semiconductor layer.

12 . The method of claim 9 , wherein the semiconductor substrate further comprises a semiconductor contact layer arranged between the semiconductor etch stop layer and the semiconductor device layer.

13 . The method of claim 1 , further comprising:
generating a structured front side etch stop layer over the semiconductor device layer to cover the dicing areas.

14 . The method of claim 13 , wherein the structured front side etch stop layer comprises a hard passivation dielectric material or a polymer material or a metal.

15 . The method of claim 1 , further comprising:
processing the semiconductor substrate to form integrated devices in the semiconductor device layer; and thereafter mounting the semiconductor substrate on a carrier with the semiconductor device layer facing the carrier.

16 . The method of claim 15 , wherein processing the semiconductor substrate is done after transforming the areas of the semiconductor device layer into dicing areas.

17 . The method of claim 15 , wherein removing the semiconductor substrate layer and the dicing areas by using the etching is done after mounting the semiconductor substrate on the carrier.

18 . The method of claim 1 , wherein removing the semiconductor substrate layer and the dicing areas comprises:
partially removing the semiconductor substrate layer by grinding such that a residual semiconductor substrate layer remains; and thereafter completely removing the residual semiconductor substrate layer and the dicing areas by using the etching.

19 . A semiconductor device including a semiconductor device chip, the semiconductor device chip comprising:
a semiconductor device layer comprising an integrated device, wherein a dicing edge of the semiconductor device layer has been formed by dopant-selective chemical etching.

20 . The semiconductor device of claim 19 , wherein the dicing edge of the semiconductor device layer has a multi-curved cross-sectional shape indicative of multiple dopant implant processes.

21 . The semiconductor device of claim 19 , further comprising:
a metal support layer supporting the semiconductor device layer, wherein the metal support layer provides a side wall protection of the semiconductor device layer.

22 . The semiconductor device of claim 19 , further comprising:
a metal support layer supporting the semiconductor device layer; and a side wall protection of the semiconductor device layer comprising a polymer material.

23 . The semiconductor device of claim 19 , wherein a thickness of the semiconductor device layer is equal to or less than 60 μm or 50 μm or 40 μm or 30 μm or 20 μm or 15 μm.

24 . The semiconductor device of claim 19 , wherein the integrated device comprises a power device.

Assignees

• Infineon Technologies Ag

Inventors

• Ernst Felix Johannes Heinrich
• Goller Bernhard
• Moder Iris
• Muri Ingo

Classifications

• H10P50/644

  Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10W70/6875

  being on a metallic substrate, e.g. insulated metal substrates [IMS] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title