Method for forming a superjunction transistor device

Patent metadata

Field	Value
Publication number	US-11189690-B2
Application number	US-201916715816-A
Country	US
Kind code	B2
Filing date	Dec 16, 2019
Priority date	Dec 17, 2018
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

A method and a transistor device are disclosed. The method includes: forming first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of a semiconductor body; and forming body regions and source regions of transistor cells in the inner region of the semiconductor body. Forming the first regions and second regions includes: forming semiconductor layers one on top of the other; and in each of the semiconductor layers and before forming a respective next one of the semiconductor layers, forming trenches in the inner region and the edge region and implanting dopant atoms into a first sidewall and a second sidewall of each trench. Implanting the dopant atoms into at least one of the semiconductor layers includes partly covering the trenches in the edge region during an implantation process.

First claim

What is claimed is:

1. A method, comprising:
forming a plurality of first regions of a first doping type and a plurality of second regions of a second doping type in an inner region and an edge region of a semiconductor body; and
forming body regions and source regions of a plurality of transistor cells in the inner region of the semiconductor body,
wherein forming the plurality of first regions and the plurality of second regions comprises:
forming a plurality of semiconductor layers one on top of the other; and
in each of the plurality of semiconductor layers and before forming a respective next one of the plurality of semiconductor layers, forming a first plurality of trenches in the inner region and a second plurality of trenches in the edge region and implanting dopant atoms into a first sidewall and a second sidewall of each of the first plurality of trenches and the second plurality of trenches,
wherein implanting the dopant atoms into at least one of the plurality of semiconductor layers comprises partly covering the second plurality of trenches in the edge region during an implantation process.

2. The method of claim 1 , wherein partly covering the second plurality of trenches in the edge region comprises:
implanting dopant atoms into the first and second sidewalls of the second plurality of trenches in a first implantation process and a second implantation process;
covering the second plurality of trenches or trench sections of the second plurality of trenches in the edge region by a protection layer; and
implanting dopant atoms into sections of the first and second sidewalls of the second plurality of trenches or trench sections of the second plurality of trenches in the edge region not covered by the protection layer in a third implantation process and a fourth implantation process.

3. The method of claim 1 , wherein partly covering the second plurality of trenches in the edge region comprises:
covering first sections of the first and second sidewalls of the second plurality of trenches in the edge region by a protection layer; and
implanting dopant into second sections of the first and second sidewalls of the second plurality of trenches in the edge region not covered by the protection layer.

4. The method of claim 3 , wherein the second plurality of trenches are elongated trenches extending in a lateral direction of the plurality of semiconductor layers, and wherein the protection layer comprises a plurality of layer sections that are spaced apart from each other in the lateral direction.

5. The method of claim 1 , wherein forming the plurality of semiconductor layers comprises forming the plurality of semiconductor layers on a carrier, and wherein the method further comprises:
after forming a lowermost one of the plurality of semiconductor layers on top of the carrier, covering the second plurality of trenches or trench sections of the second plurality of trenches in the edge region of the lowermost semiconductor layer by a protection layer; and
implanting dopant atoms of the first doping type via trench bottoms of the second plurality of trenches or trench sections of the second plurality of trenches in the edge region not covered by the protection layer into the carrier.

6. The method of claim 1 , wherein implanting dopant atoms into the first and sidewalls of each of the first plurality of trenches and the second plurality of trenches comprises:
implanting dopant atoms of both the first doping type and the second doping type into each of the first sidewalls and the second sidewalls opposite the first sidewalls.

7. The method of claim 1 , further comprising:
forming a further semiconductor layer on top of an uppermost one of the plurality of semiconductor layers.

8. The method of claim 7 , wherein forming the body regions and the source regions of the plurality of transistor cells comprises:
forming the body regions and the source regions of the plurality of transistor cells in the further semiconductor layer.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Weber Hans
• Muri Ingo
• Treiber Maximilian
• Tutuc Daniel

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10D62/058

  by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches · CPC title

• H10D62/111 Primary

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D62/107

  Buried supplementary regions, e.g. buried guard rings  (multi-RESURF H10D62/111) · CPC title

• H10D30/665

  having edge termination structures · CPC title