Transistor device and method of manufacturing

Patent metadata

Field	Value
Publication number	US-12419096-B2
Application number	US-202217590685-A
Country	US
Kind code	B2
Filing date	Feb 1, 2022
Priority date	Feb 4, 2021
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A transistor device is provided. In an example, the transistor device includes a semiconductor body having a first main surface, a second main surface opposite to the first main surface. The transistor device further includes a transistor cell array including a plurality of transistor cells. The transistor cell array includes a first load electrode over the first main surface. The first load electrode is electrically connected to the plurality of transistor cells. The transistor cell array further includes a second load electrode over the second main surface. The second load electrode is electrically connected to the plurality of transistor cells. The plurality of transistor cells includes at least one control electrode including carbon.

First claim

What is claimed is:

1. A transistor device, comprising:
a semiconductor body having a first main surface, a second main surface opposite to the first main surface, and a transistor cell array, wherein:
the transistor cell array comprises:
a plurality of transistor cells;
a first load electrode over the first main surface, wherein the first load electrode is electrically connected to the plurality of transistor cells; and
a second load electrode over the second main surface, wherein the second load electrode is electrically connected to the plurality of transistor cells;

the plurality of transistor cells comprises at least one control electrode comprising carbon;
the carbon of the at least one control electrode comprises at least one of allotropes single-layered graphene, double-layered graphene, multi-layered graphene, graphenic-like carbon or carbon nanotubes;
the at least one control electrode comprises a gate electrode;
a cap layer is over the gate electrode;
a gate dielectric separates the gate electrode from the semiconductor body;
the cap layer is at least one of (i) directly over and in contact with a vertical portion of the gate dielectric or (ii) directly over an entirety of the gate dielectric and in contact with the gate dielectric; and
an interlayer dielectric is over the cap layer, wherein the interlayer dielectric separates the gate electrode and a front side electrode.

2. The transistor device of claim 1 , wherein the cap layer comprises at least one of a nitride layer, a silicon carbide layer, or a polycrystalline silicon layer.

3. The transistor device of claim 1 , wherein the gate electrode of the at least one control electrode comprises a planar gate electrode or a trench gate electrode.

4. The transistor device of claim 3 , wherein the plurality of transistor cells is formed as stripes extending in parallel along a first lateral direction.

5. The transistor device of claim 3 , comprising a trench field electrode, wherein a ratio of a maximum lateral extension of the trench field electrode to a maximum vertical extension of the trench field electrode ranges between 0.05 and 0.5, and wherein the trench field electrode and the trench gate electrode are arranged in trenches laterally separated from one another.

6. The transistor device of claim 3 , wherein the at least one control electrode comprises a trench field electrode, and wherein the trench field electrode is arranged between the trench gate electrode and the second main surface.

7. The transistor device of claim 1 , wherein the cap layer is directly over and in contact with the vertical portion of the gate dielectric.

8. The transistor device of claim 1 , wherein the cap layer is directly over the entirety of the gate dielectric and in contact with the gate dielectric.

9. The transistor device of claim 1 , comprising a drift region, wherein the drift region is configured for a breakdown voltage between the first load electrode and the second load electrode of greater than 12 volts (V).

10. The transistor device of claim 9 , wherein the drift region is in a silicon semiconductor body, and the transistor device is an insulated gate field effect transistor or an insulated gate bipolar transistor.

11. The transistor device of claim 9 , wherein the drift region is in a silicon carbide semiconductor body, the transistor device is an insulated gate field effect transistor or an insulated gate bipolar transistor, and the at least one control electrode comprises a trench gate electrode, and wherein the transistor device comprises a shielding region of a conductivity type different from a conductivity type of the drift region, and a bottom side of the shielding region is arranged between a bottom side of a gate trench comprising the trench gate electrode and the second main surface.

12. A transistor device, comprising:
a semiconductor body having a first main surface, a second main surface opposite to the first main surface, and a transistor cell array, wherein:
the transistor cell array comprises:
a plurality of transistor cells;
a first load electrode over the first main surface, wherein the first load electrode is electrically connected to the plurality of transistor cells; and
a second load electrode over the second main surface, wherein the second load electrode is electrically connected to the plurality of transistor cells;

the plurality of transistor cells comprises at least one control electrode comprising carbon;
the carbon of the at least one control electrode comprises at least one of allotropes single-layered graphene, double-layered graphene, multi-layered graphene, graphenic-like carbon or carbon nanotubes;
the at least one control electrode comprises a gate electrode comprising at least one of a planar gate electrode or a trench gate electrode;
a cap layer over the at least one control electrode;
a gate dielectric separates the gate electrode from the semiconductor body;
the cap layer is at least one of (i) directly over and in contact with a vertical portion of the gate dielectric or (ii) directly over an entirety of the gate dielectric and in contact with the gate dielectric; and
an interlayer dielectric over the cap layer, wherein the interlayer dielectric separates the gate electrode and a front side electrode.

13. A transistor device, comprising:
a semiconductor body having a first main surface, a second main surface opposite to the first main surface, and a transistor cell array, wherein:
the transistor cell array comprises:
a plurality of transistor cells;
a first load electrode over the first main surface, wherein the first load electrode is electrically connected to the plurality of transistor cells; and
a second load electrode over the second main surface, wherein the second load electrode is electrically connected to the plurality of transistor cells;

the plurality of transistor cells comprises at least one control electrode comprising carbon;
the carbon of the at least one control electrode comprises at least one of allotropes single-layered graphene, double-layered graphene, multi-layered graphene, graphenic-like carbon or carbon nanotubes;
the at least one control electrode comprises a gate electrode;
a cap layer is over the gate electrode;
a gate dielectric separates the gate electrode from the semiconductor body;
the cap layer is at least one of (i) directly over and in contact with a vertical portion of the gate dielectric or (ii) directly over an entirety of the gate dielectric and in contact with the gate dielectric;
an interlayer dielectric is over the cap layer; and
a drift region, wherein the drift region is configured for a breakdown voltage between the first load electrode and the second load electrode of greater than 12 volts (V), wherein the drift region is in a silicon carbide semiconductor body, the transistor device is an insulated gate field effect transistor or an insulated gate bipolar transistor, and the at least one control electrode comprises a trench gate electrode, and wherein the transistor device comprises a shielding region of a conductivity type different from a conductivity type of the drift region, and a bottom side of the shielding region is arranged between a bottom side of a gate trench comprising the trench gate electrode and the second main surface.

14. The transistor device of claim 13 , wherein the cap layer comprises at least one of a nitride layer, a silicon carbide layer, or a polycrystalline silicon layer.

15. The transistor device of claim 13 , wherein the gate electrode of the at least one control electrode comprises a planar gate e

Assignees

• Infineon Technologies Ag

Inventors

• Siemieniec Ralf
• Muri Ingo
• Schloesser Till
• Schulze Hans-Joachim
• Storbeck Olaf

Classifications

• H10W90/00

  Package configurations · CPC title

• H10D64/01366

  the semiconductor being silicon carbide · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title