Semiconductor device having semiconductor device elements in a semiconductor layer

US12107130B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12107130-B2
Application numberUS-202117235989-A
CountryUS
Kind codeB2
Filing dateApr 21, 2021
Priority dateMay 9, 2018
Publication dateOct 1, 2024
Grant dateOct 1, 2024

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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A semiconductor device includes a semiconductor substrate having a first dopant and a second dopant. A covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant. The semiconductor device further includes a semiconductor layer on the semiconductor substrate and semiconductor device elements in the semiconductor layer. A vertical concentration profile of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface.

First claim

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What is claimed is: 1. A semiconductor device, comprising: a semiconductor substrate comprising a first dopant and a second dopant, wherein a covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant; a semiconductor layer on the semiconductor substrate; and semiconductor device elements in the semiconductor layer, wherein a vertical concentration profile of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface, wherein the vertical concentration profile N1(y) of the first dopant and a vertical concentration profile N2(y) of the second dopant satisfy: ∫ 0 t ❘ "\[LeftBracketingBar]" N ⁢ 1 ⁢ ( y ) - N ⁢ 2 ⁢ ( y ) ❘ "\[RightBracketingBar]" ⁢ dy ∫ 0 t N ⁢ 1 ⁢ ( y ) ⁢ d ⁢ y < 100 ⁢ % , where t is a final thickness of the semiconductor substrate. 2. The semiconductor device of claim 1 , wherein an average concentration of the vertical concentration profile of the first dopant between the interface and the surface of the semiconductor substrate opposite to the interface is in a range from 5×10 18 cm −3 to 5×10 20 cm −3 . 3. The semiconductor device of claim 1 , wherein the first dopant is one element selected from the group consisting of arsenic, phosphorus, and antimony, and wherein the second dopant is a different element selected from the group consisting of arsenic, phosphorus and antimony. 4. The semiconductor device of claim 1 , wherein the first dopant is one element selected from the group consisting of boron, aluminum, and gallium, and wherein the second dopant is a different element selected from the group consisting of boron, aluminum, and gallium. 5. The semiconductor device of claim 1 , wherein the vertical concentration profile of the first dopant and a vertical concentration profile of the second dopant are superimposed. 6. The semiconductor device of claim 1 , wherein silicon is the material of the semiconductor substrate, wherein the first dopant is phosphorus, and wherein the second dopant is arsenic. 7. The semiconductor device of claim 1 , wherein silicon is the material of the semiconductor substrate, wherein the first dopant is arsenic, and wherein the second dopant is phosphorus. 8. The semiconductor device of claim 1 , wherein a vertical extension of the first dopant into the semiconductor substrate from a first main surface of the semiconductor substrate ends at a bottom side of a first semiconductor substrate portion at a first vertical distance to the first main surface. 9. The semiconductor device of claim 8 , wherein the first dopant is absent or at least less than 10 14 doping atoms per cm 3 in a second substrate portion that directly adjoins the first semiconductor substrate portion at the bottom side. 10. The semiconductor device of claim 8 , wherein the first vertical distance t1 is in a range from 2 μm to 50 μm. 11. The semiconductor device of claim 10 , wherein the first vertical distance t1 is in a range from 5 μm to 30 μm. 12. The semiconductor device of claim 1 , wherein a material of the semiconductor layer differs from the material of the semiconductor substrate. 13. The semiconductor device of claim 1 , wherein the first dopant causes an increase of a lattice constant with respect to the semiconductor substrate, and wherein the second dopant counteracts the increase. 14. The semiconductor device of claim 1 , wherein the first dopant causes a decrease of a lattice constant with respect to the semiconductor substrate, and wherein the second dopant counteracts the decrease. 15. The semiconductor device of claim 1 , wherein a vertical concentration profile of the second dopant decreases along at least 80% of the distance between the interface to the surface of the semiconductor substrate opposite to the interface. 16. The semiconductor device of claim 1 , wherein the second dopant constitutes a background doping of the semiconductor substrate in a range from 10 18 cm −3 to 10 21 cm −3 .

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What does patent US12107130B2 cover?
A semiconductor device includes a semiconductor substrate having a first dopant and a second dopant. A covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent ato…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10P32/1204. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).