Silicon-on-insulator die support structures and related methods
US-2020258751-A1 · Aug 13, 2020 · US
Method of manufacturing semiconductor chips having a side wall sealing
US12525499B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12525499-B2 |
| Application number | US-202017620342-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 18, 2020 |
| Priority date | Jun 21, 2019 |
| Publication date | Jan 13, 2026 |
| Grant date | Jan 13, 2026 |
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- Title
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Abstract
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A method of manufacturing semiconductor chips having a side wall sealing is described. The method includes forming dicing trenches in a semiconductor wafer. The side walls of the dicing trenches are anodized to generate an anodic oxide layer at the side walls of the dicing trenches. Semiconductor chips are separated from the semiconductor wafer.
First claim
Opening claim text (preview).
The invention claimed is: 1 . A method of manufacturing semiconductor chips having a side wall sealing, the method comprising: forming dicing trenches in a semiconductor wafer; anodizing side walls of the dicing trenches to generate an anodic oxide layer at the side walls of the dicing trenches, wherein a temperature of an electrolyte during the anodizing is equal to or higher than 70° C.; and separating the semiconductor chips from the semiconductor wafer. 2 . The method of claim 1 , further comprising: implanting an n-type dopant or a p-type dopant into the side walls of the dicing trenches before anodizing. 3 . The method of claim 1 , further comprising: implanting hydrogen into the side walls of the dicing trenches before anodizing. 4 . The method of claim 1 , further comprising: illuminating the side walls of the dicing trenches during anodizing. 5 . The method of claim 1 , wherein the separating comprises: thinning the semiconductor wafer after the anodizing, at a semiconductor wafer surface opposite the dicing trenches. 6 . The method of claim 1 , further comprising: filling the dicing trenches with an organic resin after the anodizing. 7 . The method of claim 6 , wherein the separating comprises: singulating the semiconductor chips by laser cutting through the organic resin. 8 . The method of claim 1 , further comprising: depositing an electrode metal material or a solder material over the semiconductor wafer after the anodizing. 9 . The method of claim 1 , wherein forming the dicing trenches comprises blade dicing or plasma dicing. 10 . The method of claim 1 , further comprising: generating a mask layer over the semiconductor wafer after forming the dicing trenches; and patterning the mask layer to expose the dicing trenches, wherein the anodizing of the side walls of the dicing trenches is performed by using the patterned mask layer. 11 . The method of claim 1 , further comprising: generating a mask layer over the semiconductor wafer before forming the dicing trenches; and patterning the mask layer to expose dicing trench streets of the semiconductor wafer, wherein the dicing trenches are formed by plasma dicing by using the patterned mask layer, wherein the anodizing of the side walls of the dicing trenches is performed by using the patterned mask layer.
Assignees
Inventors
Classifications
Cutting or separating of wafers, substrates or parts of devices · CPC title
- H10P52/00Primary
Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title
Formation by anodic treatments, e.g. anodic oxidation · CPC title
forming a chip-scale package [CSP] · CPC title
Bond pads specially adapted therefor · CPC title
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Frequently asked questions
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- What does patent US12525499B2 cover?
- A method of manufacturing semiconductor chips having a side wall sealing is described. The method includes forming dicing trenches in a semiconductor wafer. The side walls of the dicing trenches are anodized to generate an anodic oxide layer at the side walls of the dicing trenches. Semiconductor chips are separated from the semiconductor wafer.
- Who is the assignee on this patent?
- Infineon Technologies Austria Ag
- What technology area does this patent fall under?
- Primary CPC classification H10P52/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 13 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).