Method for partially removing a semiconductor wafer

Patent metadata

Field	Value
Publication number	US-11404262-B2
Application number	US-201916677801-A
Country	US
Kind code	B2
Filing date	Nov 8, 2019
Priority date	Nov 23, 2018
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

A method includes: in a semiconductor wafer including a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a first surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10 −2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer.

First claim

What is claimed is:

1. A method, comprising:
in a semiconductor wafer comprising a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a first surface into the first semiconductor layer; and
removing the porous region by an etching process,
wherein a doping concentration of the second semiconductor layer is less than 10 −2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer,
wherein forming the porous region comprises bringing in contact a porosifying agent with the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent,
wherein applying the voltage comprises applying the voltage such that a current density of a current associated with the voltage, at least in sections, decreases at the first surface between a center and an edge region of the first semiconductor layer,
wherein at least one insulating element is arranged above the edge region of the first semiconductor layer and configured to reduce an active height of the porosifying agent above the edge region as compared to the center of the first semiconductor layer.

2. The method of claim 1 , wherein the porous region is formed such that the porous region covers at least 80% of the volume of the first semiconductor layer.

3. The method of claim 1 , wherein the porous region is formed such that, in a vertical direction of the first layer, the porous region extends from the first surface to the second semiconductor layer, and wherein in lateral directions of the first semiconductor layer, the porous region extends from a center towards an edge surface of the first semiconductor layer.

4. The method of claim 1 , wherein bringing in contact the porosifying agent with the first semiconductor layer comprises:
attaching a tubular element to the first surface; and
partially filling a reservoir formed by the tubular element and the first surface with the porosifying agent.

5. The method of claim 1 , wherein applying the voltage comprises applying the voltage between the first electrode and the edge region of the first semiconductor layer.

6. The method of claim 1 , wherein the first electrode is plate-shaped.

7. The method of claim 1 , wherein the first electrode is needle-shaped.

8. The method of claim 1 , wherein the first electrode is such that a distance between the first electrode and the first surface increases towards the edge region of the first semiconductor layer.

9. The method of claim 1 , wherein the first electrode is conical.

10. The method of claim 1 , wherein the first electrode is spiral-shaped.

11. The method of claim 1 , wherein the first electrode comprises several concentric rings.

12. The method of claim 1 , wherein the at least one insulating element comprises a ring adjoining the tubular element and extending inwardly from the tubular element.

13. The method of claim 12 , wherein the ring has a first surface facing the first semiconductor layer, and wherein an angle between a plane parallel to the first surface of the first semiconductor layer and the first surface of the ring is between 0° and 45°.

14. The method of claim 12 , wherein the ring has a first dimension in a direction perpendicular to the tubular element, wherein the tubular element has an inner radius, and wherein a ratio between the first dimension of the ring and the inner radius of the tubular element is between 0.05 and 0.7.

15. The method of claim 1 , wherein the active height of the porosifying agent above the edge region is less than 1 cm.

16. The method of claim 1 , wherein bringing in contact the porosifying agent with the first semiconductor layer comprises:
gradually immerging the semiconductor wafer into a container comprising the porosifying agent such that an area of the first surface that comes into contact with the porosifying agent increases during the porosification process over time.

17. The method of claim 1 , wherein the first surface is planar.

18. The method of claim 1 , wherein a thickness of the first semiconductor layer increases towards an edge of the first semiconductor layer.

19. The method of claim 1 , further comprising:
forming a plurality of transistor cells in the second semiconductor layer before forming the porous region and removing the porous region.

20. The method of claim 19 , further comprising:
forming a drain region in the second semiconductor layer after removing the porous region.

21. The method of claim 1 , wherein the semiconductor wafer further comprises a third semiconductor layer on top of the second semiconductor layer, and wherein the second semiconductor layer has a thickness less than 10 micrometers, less than 5 micrometers, or less than 1 micrometer.

22. The method of claim 21 , further comprising:
forming a plurality of transistor cells in the third semiconductor layer before forming the porous region.

23. The method of claim 22 , further comprising:
removing the second semiconductor layer; and
forming a drain region in the third semiconductor layer after removing the porous region.

24. The method of claim 22 , further comprising:
forming a drain region in the second semiconductor layer after removing the porous region.

Assignees

• Infineon Technologies Ag

Inventors

• Friedler Sophia
• Goller Bernhard
• Moder Iris
• Muri Ingo

Classifications

• H10P95/70

  Chemical treatments · CPC title

• H10P90/126

  by chemical etching · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/20

  Dry etching; Plasma etching; Reactive-ion etching · CPC title

• H10P90/15 Primary

  by making porous regions on the surface · CPC title