Method for producing a superjunction device

Patent metadata

Field	Value
Publication number	US-11652138-B2
Application number	US-202117330681-A
Country	US
Kind code	B2
Filing date	May 26, 2021
Priority date	May 27, 2020
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

A method for producing a semiconductor device includes forming transistor cells in a semiconductor body, each cell including a drift region separated from a source region by a body region, a gate electrode dielectrically insulated from the body region, and a compensation region of a doping type complementary to the doping type of the drift region and extending from a respective body region into the drift region in a vertical direction. Forming the drift and compensation regions includes performing a first implantation step, thereby implanting first and second type dopant atoms into the semiconductor body, wherein an implantation dose of at least one of the first type dopant atoms and the second type dopant atoms for each of at least two sections of the semiconductor body differs from the implantation dose of the corresponding type of dopant atoms of at least one other section of the at least two sections.

First claim

What is claimed is:

1. A method for producing a semiconductor device, the method comprising:
forming a plurality of transistor cells in a semiconductor body, each transistor cell comprising a source region, a body region, a drift region separated from the source region by the body region, a gate electrode dielectrically insulated from the body region, and a compensation region of a doping type complementary to the doping type of the drift region and extending from a respective body region into the drift region in a vertical direction, wherein forming a plurality of the drift regions and a plurality of the compensation regions comprises:
forming a semiconductor arrangement, wherein forming the semiconductor arrangement comprises:
forming a semiconductor layer; and
forming a plurality of trenches in a first surface of the semiconductor layer; and

performing a first implantation step, thereby implanting dopant atoms of a first type and dopant atoms of a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches, wherein an implantation dose of at least one of the first type dopant atoms and the second type dopant atoms for each of at least two sections of the semiconductor body differs from the implantation dose of the corresponding type of dopant atoms of at least one other section of the at least two sections, wherein the at least two sections are arranged successively in a horizontal direction.

2. The method of claim 1 , wherein:
the implantation dose of the first type dopant atoms is essentially homogenous within each of the at least two sections; and
the implantation dose of the second type dopant atoms is essentially homogenous within each of the at least two sections.

3. The method of claim 1 , wherein within at least one of the at least two sections of the semiconductor body, the implantation dose of the first type dopant atoms differs from the implantation dose of the second type dopant atoms.

4. The method of claim 1 , wherein the different sections of the semiconductor body are arranged in a radially symmetrical pattern, and therefore, performing the first implantation step results in a radially symmetrical distribution of at least one of the first type dopant atoms and the second type dopant atoms within the semiconductor body.

5. The method of claim 1 , further comprising:
performing a second implantation step, thereby implanting dopant atoms of the first type and dopant atoms of the second type into the semiconductor body,
wherein an implantation dose of the first type dopant atoms of each of the at least two sections is equal to the implantation dose of the corresponding type of dopant atoms of each of the other sections; and
an implantation dose of the second type dopant atoms of each of the at least two sections is equal to the implantation dose of the corresponding type of dopant atoms of each of the other sections.

6. The method of claim 5 , wherein
the first implantation step is performed after the second implantation step.

7. The method of claim 5 , wherein:
during the first implantation step, about 2% to 10% of a total implantation dose of each of the first type dopant atoms and the second type dopant atoms are implanted for each of the at least two sections; and
during the second implantation step, about 90% to 98% of a total implantation dose of each of the first type dopant atoms and the second type dopant atoms are implanted for each of the at least two sections, such that after performing both the first and the second implantation step, 100% of the total implantation dose of each of the first type dopant atoms and the second type dopant atoms are implanted for each of the at least two sections.

8. The method of claim 1 , wherein forming the plurality of drift regions and the plurality of compensation regions further comprises:
forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements comprises:
forming a semiconductor layer;
forming a plurality of trenches in a first surface of the semiconductor layer; and
implanting the dopant atoms of at least one of the first type and the second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.

9. The method of claim 8 , wherein forming the semiconductor layer comprises epitaxially growing the semiconductor layer.

10. The method of claim 8 , wherein implanting the dopant atoms comprises:
implanting dopant atoms of the first type into the first sidewall; and
implanting dopant atoms of the second type into the second sidewall.

11. The method of claim 8 , wherein implanting the dopant atoms comprises:
implanting dopant atoms of both the first type and the second type into at least one of the first sidewall and the second sidewall.

12. The method of claim 1 , further comprising:
annealing the semiconductor body to diffuse the dopant atoms.

13. The method of claim 1 , wherein each of the at least two sections comprises a subset of the plurality of transistor cells.

14. The method of claim 1 , wherein
the first implantation step comprises implanting the first type dopant atoms during a first sub-process and implanting the second type dopant atoms in a separate second sub-process.

15. The method of claim 14 , wherein the first implantation step comprises performing the first sub-process after the second sub-process.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Muri Ingo
• Schubert Felix
• Tutuc Daniel
• Weber Hans

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P32/12

  between a solid phase and a gaseous phase · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title