Multi-reticle device with electrical and optical stitching
US-2026076264-A1 · Mar 12, 2026 · US
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Modi Mitul patents
Modi Mitul is listed as an inventor on 62 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Modi Mitul |
| Total patents | 62 |
| First publication | Jun 29, 2017 |
| Latest publication | Mar 12, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Keep out zone with hydrophobic surface for integrated circuit (IC) package
US-12575415-B2 · Mar 10, 2026 · US
Reconstituted wafer-scale devices using semiconductor strips
US-2026026408-A1 · Jan 22, 2026 · US
Ultra-thin, hyper-density semiconductor packages
US-2025391754-A1 · Dec 25, 2025 · US
Ultra-thin, hyper-density semiconductor packages
US-12476174-B2 · Nov 18, 2025 · US
3d stacked i/o chiplet on optical interposer for high bandwidth applications
US-2025321909-A1 · Oct 16, 2025 · US
Nested glass packaging architecture for hybrid electrical and optical communication devices
US-12422615-B2 · Sep 23, 2025 · US
Ultra-thin, hyper-density semiconductor packages
US-12406914-B2 · Sep 2, 2025 · US
Photonic integrated circuit packaging architectures
US-12392970-B2 · Aug 19, 2025 · US
No mold shelf package design and process flow for advanced package architectures
US-2025192101-A1 · Jun 12, 2025 · US
Recent patents
Latest publications not already listed above.
Mold shelf package design and process flow for advanced package architectures
US-12261150-B2 · Mar 25, 2025 · US
Open cavity bridge co-planar placement architectures and processes
US-12176268-B2 · Dec 24, 2024 · US
Chip-scale package architectures containing a die back side metal and a solder thermal interface material
US-2024332112-A1 · Oct 3, 2024 · US
No mold shelf package design and process flow for advanced package architectures
US-12087731-B2 · Sep 10, 2024 · US
Dummy die structures of a packaged integrated circuit device
US-12068222-B2 · Aug 20, 2024 · US
Chip-scale package architectures containing a die back side metal and a solder thermal interface material
US-12040246-B2 · Jul 16, 2024 · US
Open cavity bridge power delivery architectures and processes
US-12027448-B2 · Jul 2, 2024 · US
No mold shelf package design and process flow for advanced package architectures
US-2024136326-A1 · Apr 25, 2024 · US
Substrate with thermal insulation
US-11942393-B2 · Mar 26, 2024 · US
No mold shelf package design and process flow for advanced package architectures
US-11901333-B2 · Feb 13, 2024 · US
Ultra-thin, hyper-density semiconductor packages
US-2024030116-A1 · Jan 25, 2024 · US
Active package cooling structures using molded substrate packaging technology
US-11735495-B2 · Aug 22, 2023 · US
No mold shelf package design and process flow for advanced package architectures
US-2023238355-A1 · Jul 27, 2023 · US
Stacked die cavity package
US-11705377-B2 · Jul 18, 2023 · US
Ultra-thin, hyper-density semiconductor packages
US-2023138543-A1 · May 4, 2023 · US
Photonic integrated circuit packaging architectures
US-2023089494-A1 · Mar 23, 2023 · US
Photonic integrated circuit packaging architectures
US-2023092821-A1 · Mar 23, 2023 · US
Wideband multi-pin edge connector for radio frequency front end module
US-11611164-B2 · Mar 21, 2023 · US
Nested glass packaging architecture for hybrid electrical and optical communication devices
US-2023080454-A1 · Mar 16, 2023 · US
Coupled cooling fins in ultra-small systems
US-11574851-B2 · Feb 7, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 59 |
| Lightmatter Inc | 3 |
| Sk Hynix Nand Product Solutions Corp | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/00 | 42 |
| H10W90/724 | 41 |
| H10W90/701 | 30 |
| H10W74/15 | 30 |
| H10W74/117 | 27 |