Open cavity bridge co-planar placement architectures and processes

Patent metadata

Field	Value
Publication number	US-12176268-B2
Application number	US-202016828405-A
Country	US
Kind code	B2
Filing date	Mar 24, 2020
Priority date	Mar 24, 2020
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.

First claim

What is claimed is:

1. An electronic apparatus, comprising:
a package substrate having alternating metallization layers and dielectric layers, the package substrate comprising:
a first plurality of substrate pads and a second plurality of substrate pads;
an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides; and a plurality of conductive vias directly coupling the metallization layers and the substrate pads; and

a bridge die in the open cavity, the bridge die comprising a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces;
an adhesive layer coupling the bridge die to the bottom of the open cavity, the adhesive layer beneath and extending laterally beyond outermost sides of the bridge die; and
a gap laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.

2. The electronic apparatus of claim 1 , further comprising:
a first die coupled to the first plurality of substrate pads and the first plurality of bridge pads; and
a second die coupled to the second plurality of substrate pads and the second plurality of bridge pads, the second die coupled to the first die by the conductive traces of the bridge die.

3. The electronic apparatus of claim 2 , wherein the first die is coupled to the first plurality of substrate pads and the first plurality of bridge pads by a first plurality of solder structures, and the second die is coupled to the second plurality of substrate pads and the second plurality of bridge pads by a second plurality of solder structures.

4. The electronic apparatus of claim 2 , further comprising:
a board coupled to a side of the package substrate opposite the first die and the second die.

5. The electronic apparatus of claim 1 , wherein adjacent pads of the first plurality of bridge pads and adjacent pads of the second plurality of bridge pads have a first pitch, and wherein adjacent pads of the first plurality of substrate pads and adjacent pads of the second plurality of substrate pads have a second pitch greater than the first pitch.

6. The electronic apparatus of claim 5 , wherein the first pitch is less than approximately 100 μm and the second pitch is greater than approximately 100 μm.

Assignees

• Intel Corp

Inventors

• Karhade Omkar
• Raorane Digvijay
• Agraharam Sairam
• Deshpande Nitin
• Modi Mitul
• Dubey Manish
• Cetegen Edvin

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W70/411

  Chip-supporting parts, e.g. die pads · CPC title

• H10W70/65 Primary

  Shapes or dispositions of interconnections · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/722

  between stacked chips · CPC title