Active package cooling structures using molded substrate packaging technology

Patent metadata

Field	Value
Publication number	US-11735495-B2
Application number	US-201916287653-A
Country	US
Kind code	B2
Filing date	Feb 27, 2019
Priority date	Feb 27, 2019
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. Fluid conduits may be at least partially defined by an interconnect trace comprising a metal. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.

First claim

What is claimed is:

1. A microelectronic device package structure, comprising:
a substrate structure comprising one or more traces adjacent to a mold material, wherein the traces comprise a metal;
an integrated circuit (IC) die physically coupled to the substrate structure, and electrically coupled to at least one of the traces; and
a fluid conduit within the substrate structure, wherein at least a portion of the fluid conduit comprises the metal, and wherein the fluid conduit comprises an inlet to receive a fluid into the substrate structure and an outlet to discharge the fluid from the substrate structure with a length of the fluid conduit therebetween.

2. The microelectronic device package structure of claim 1 , wherein the IC die is over at least a portion of the fluid conduit, and wherein the length of the fluid conduit is greater than a length of the IC die.

3. The microelectronic device package structure of claim 1 , wherein the fluid conduit comprises a lateral run between a first conductive via structure and a second conductive via structure, and wherein the first conductive via structure is to convey the fluid to the lateral run, and the second conductive via structure is to convey the fluid from the lateral run.

4. A microelectronic device package structure, comprising:
a substrate structure comprising one or more traces adjacent to a mold material, wherein the traces comprise a metal;
an integrated circuit (IC) die physically coupled to the substrate structure, and electrically coupled to at least one of the traces; and
a fluid conduit within the substrate structure, wherein at least a portion of the fluid conduit comprises the metal, and wherein the fluid conduit comprises a heat pipe sealed within the substrate structure.

5. A microelectronic device package structure, comprising:
a substrate structure comprising one or more traces adjacent to a mold material, wherein the traces comprise a metal;
an integrated circuit (IC) die physically coupled to the substrate structure, and electrically coupled to at least one of the traces; and
a fluid conduit within the substrate structure, wherein at least a portion of the fluid conduit comprises the metal, and wherein the substrate structure comprises a first substrate and a second substrate, the first substrate bonded to the second substrate, and wherein the fluid conduit is between the first substrate and the second substrate.

6. The microelectronic device package structure of claim 5 , wherein:
the IC die is bonded to the first substrate; and
the fluid conduit comprises a metal trace of the first substrate directly bonded, or attached by solder, to a metal trace of the second substrate.

7. The microelectronic device package structure of claim 5 , wherein the fluid conduit further comprises solder bonded to the metal.

8. The microelectronic device package structure of claim 5 , wherein the fluid conduit comprises a first conduit having a sidewall comprising a first trace and a second conduit having a sidewall comprising a second trace.

9. The microelectronic device package structure of claim 8 , wherein the first and second conduits are separated from each other by the first and second traces, and wherein the IC die is electrically coupled to a conductive interconnect located between the first trace and the second trace.

10. The microelectronic device package structure of claim 8 , wherein each of a first sidewall, a second sidewall, a top side and a bottom side of the fluid conduit comprises a conductive trace.

11. The microelectronic device package structure of claim 10 , wherein at least one of the first sidewall, the second sidewall, the top side or the bottom side of the fluid conduit is adjacent the mold material.

12. The microelectronic device package structure of claim 10 ,
wherein:
the substrate structure comprises a first mold material;
the IC die is embedded within a second mold material;
the IC die is coupled to the substrate structure through solder features; and
the fluid conduit is separated from the IC die by at least the first mold material.

13. The microelectronic device package structure of claim 10 , wherein at least one of the first sidewall or the second sidewall comprises one or more of copper or solder.

14. The microelectronic device package structure of claim 8 , wherein the fluid conduit comprises a through-substrate via structure, and wherein a sidewall of the through-substrate via structure comprises a first interconnect trace level of the substrate structure and a second interconnect trace level of the substrate structure, in contact with the first interconnect trace level.

Assignees

• Intel Corp

Inventors

• Karhade Omkar
• Modi Mitul
• Cetegen Edvin
• Uppal Aastha

Classifications

• H10W40/73

  for cooling by change of state · CPC title

• H10W40/037

  Assembling together parts thereof · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title