Chip-scale package architectures containing a die back side metal and a solder thermal interface material

Patent metadata

Field	Value
Publication number	US-2024332112-A1
Application number	US-202418744108-A
Country	US
Kind code	A1
Filing date	Jun 14, 2024
Priority date	Sep 25, 2020
Publication date	Oct 3, 2024
Grant date	—

Abstract

An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10 −6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

First claim

We claim:

1 . An integrated circuit (IC) package structure, comprising:
a die having a front side and a backside; a first material comprising a first metal over the backside, wherein the first material has a thermal conductivity of not less than 40 W/mK; and a second material comprising a second metal over the first material, wherein the second material has a coefficient of thermal expansion (CTE) of not less than 18×10 −6 m/mK, and wherein an interface between the first material and the second material comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

2 . The IC package structure of claim 1 , wherein the first metal comprises copper, indium, gallium, aluminum, silver, or tin.

3 . The IC package structure of claim 1 , wherein the second metal comprises copper, zinc, aluminum, or nickel.

4 . The IC package structure of claim 1 , wherein the first material comprises a plurality of filler particles embedded within the first metal, wherein the filler particles comprise nickel, copper, silver, gold, cobalt, or aluminum.

5 . The IC package structure of claim 1 , wherein the first material and the second material both cover substantially all of the backside of the die, or the first material is within a recess of the second material.

6 . The IC package structure of claim 1 , wherein the second material has a first z-height and the first material has a second z-height less than the first z-height, wherein the first z-height is 500 microns or less, and the second z-height is 150 microns or less.

7 . The IC package structure of claim 1 , wherein the interface comprises any one of a first IMC comprising copper and indium, a second IMC comprising copper, indium, and silver, or a third IMC comprising copper, indium, and tin.

8 . The IC package structure of claim 7 , wherein the interface comprises one layer comprising any of the first IMC, the second IMC, or the third IMC, or the interface comprises at least two layers, wherein each of the at least two layers comprises any one of the first IMC, the second IMC, or the third IMC.

9 . The IC package structure of claim 1 , wherein a second interface between the first material and a third material comprises a second IMC.

10 . The IC package structure of claim 1 , further comprising:
a package substrate coupled to the die; and a board coupled to the package substrate.

11 . An integrated circuit (IC) package structure, comprising:
a die having a front side and a backside; a first material comprising a first metal over the backside, wherein the first material comprises a plurality of filler particles embedded within the first metal; and a second material comprising a second metal over the first material, wherein an interface between the first material and the second material comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

12 . The IC package structure of claim 11 , wherein the first metal comprises copper, indium, gallium, aluminum, silver, or tin.

13 . The IC package structure of claim 11 , wherein the second metal comprises copper, zinc, aluminum, or nickel.

14 . The IC package structure of claim 11 , wherein the filler particles comprise nickel, copper, silver, gold, cobalt, or aluminum.

15 . The IC package structure of claim 11 , wherein the first material and the second material both cover substantially all of the backside of the die, or the first material is within a recess of the second material.

16 . The IC package structure of claim 11 , wherein the second material has a first z-height and the first material has a second z-height less than the first z-height, wherein the first z-height is 500 microns or less, and the second z-height is 150 microns or less.

17 . The IC package structure of claim 11 , wherein the interface comprises any one of a first IMC comprising copper and indium, a second IMC comprising copper, indium, and silver, or a third IMC comprising copper, indium, and tin.

18 . The IC package structure of claim 17 , wherein the interface comprises one layer comprising any of the first IMC, the second IMC, or the third IMC, or the interface comprises at least two layers, wherein each of the at least two layers comprises any one of the first IMC, the second IMC, or the third IMC.

19 . The IC package structure of claim 11 , wherein a second interface between the first material and a third material comprises a second IMC.

20 . The IC package structure of claim 11 , further comprising:
a package substrate coupled to the die; and a board coupled to the package substrate.

Assignees

• Intel Corp

Inventors

• Das Mahapatra Susmriti
• Sankarasubramanian Malavarayan
• Howell Shenavia
• Harper John
• Modi Mitul

Classifications

• H10W72/07234

  Using a reflow oven · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title