Nested glass packaging architecture for hybrid electrical and optical communication devices

Patent metadata

Field	Value
Publication number	US-12422615-B2
Application number	US-202117473694-A
Country	US
Kind code	B2
Filing date	Sep 13, 2021
Priority date	Sep 13, 2021
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

First claim

The invention claimed is:

1. A substrate comprising:
a core of glass;
alternating layers of dielectric and conductive traces on either side of the core, wherein:
the core comprises a waveguide having a first endpoint on a first side of the core, and a second endpoint on a second side of the core, and
the first side is orthogonal to the second side; and

TGVs through the dielectric and the core, wherein the TGVs electrically couple a third side of the substrate with a fourth side of the substrate opposite to the third side.

2. The substrate of claim 1 , further comprising an optical via aligned with the waveguide and configured to route optical signals between the waveguide and the third side of the substrate, wherein the third side is parallel to and spaced apart from the second side.

3. The substrate of claim 1 , further comprising:
a first set of conductive contacts on the third side configured to couple to a PIC or EIC with FLIs; and
a second set of conductive contacts on the fourth side configured to couple to another substrate with MLIs, wherein the another substrate couples to a PCB with SLIs.

4. The substrate of claim 1 , wherein the core comprises a cavity having an IC die that provides electrical coupling between components coupled to the substrate.

5. The substrate of claim 4 , wherein the IC die comprises TSVs.

6. The substrate of claim 3 , wherein the substrate is smaller than the another substrate.

7. The substrate of claim 4 , wherein the cavity is a blind cavity.

8. The substrate of claim 4 , wherein an insulator fills a space around the IC die in the cavity.

9. The substrate of claim 4 , wherein the IC die is attached to the cavity with an adhesive.

10. The substrate of claim 4 , wherein the IC die facilitates power, ground and signal connection between components coupled to the substrate.

11. A substrate comprising:
a core of glass;
alternating layers of dielectric and conductive traces on either side of the core, wherein:
the core comprises a waveguide having a first endpoint on a first side of the core, and a second endpoint on a second side of the core, and
the first side is orthogonal to the second side;

an optical via aligned with the waveguide and configured to route optical signals between the waveguide and a third side of the substrate, wherein the third side is parallel to and spaced apart from the second side, wherein the optical via is configured to interface with an optical lens attached to the second side of the substrate and aligned with the optical via.

Assignees

• Intel Corp

Inventors

• Pietambaram Srinivas V
• Marin Brandon C
• Mallik Debendra
• Ibrahim Tarek A
• Ecton Jeremy
• Karhade Omkar G
• Penmecha Bharat Prasad
• Li Xiaoqian
• Deshpande Nitin A
• Modi Mitul
• Nie Bai

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title