Substrate with thermal insulation

Patent metadata

Field	Value
Publication number	US-11942393-B2
Application number	US-202016781563-A
Country	US
Kind code	B2
Filing date	Feb 4, 2020
Priority date	Feb 4, 2020
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate;
a first region of the substrate to be coupled with a die;
a second region of the substrate adjacent to the first region of the substrate, wherein the first region and the second region are separate and distinct regions and the second region has a lower thermal conductivity than the first region, and wherein the second region comprises a plurality of discrete portions; and
wherein the second region is to thermally insulate a portion of the first region when the die is coupled to the first region.

2. The apparatus of claim 1 , wherein the first region includes one or more thermally conductive layers in the substrate.

3. The apparatus of claim 2 , wherein the second region includes fewer thermally conductive layers then the first region.

4. The apparatus of claim 2 , wherein the conductive layers are metallic layers.

5. The apparatus of claim 4 , wherein the metallic layers include copper.

6. The apparatus of claim 1 , wherein the second region is a volume removed from the substrate.

7. The apparatus of claim 1 , wherein the second region is a dielectric.

8. The apparatus of claim 1 , further comprising a third region of the substrate adjacent to the first region of the substrate, wherein the first region, the second region, and the third region are different regions and the third region has a lower thermal conductivity than the first region.

9. A package, comprising:
a substrate;
a die directly coupled with a first region of the substrate;
a second region of the substrate adjacent to the first region of the substrate, wherein the first region and the second region are different regions and the second region has a lower thermal conductivity than the first region, and wherein the second region comprises a plurality of discrete portions; and
wherein the second region is to reduce thermal energy loss in the first region when the die is coupled to the first region.

10. The package of claim 9 , wherein the die coupled with the first region of the substrate further includes a solder connection; and
wherein the solder connection is proximate to the second region.

11. The package of claim 10 , wherein the solder connection is proximate to a corner of the substrate.

12. The package of claim 10 , wherein the solder connection is at a corner or an edge of the die.

13. The package of claim 9 , wherein the first region includes one or more thermally conductive layers in the substrate and wherein the second region includes fewer conductive layers then the first region.

14. The package of claim 9 , wherein the thermally conductive layers are metallic layers that include copper.

15. The package of claim 9 , wherein the first region and the second region are arranged to retain thermal energy in the first region during thermal compression bonding of the die to the substrate.

16. The package of claim 15 , wherein the second region is disposed between the first region and an edge of the substrate.

Assignees

• Intel Corp

Inventors

• Li Wei
• Cetegen Edvin
• Haehn Nicholas S
• Modi Mitul
• Neal Nicholas

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07232

  Compression bonding, e.g. thermocompression bonding · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title