Stacked die cavity package

Patent metadata

Field	Value
Publication number	US-11705377-B2
Application number	US-202217720202-A
Country	US
Kind code	B2
Filing date	Apr 13, 2022
Priority date	Dec 27, 2016
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

First claim

We claim:

1. A method comprising:
forming a substrate with a cavity defining a lower surface and an upper surface parallel to the lower surface;
forming solder spheres on the upper surface;
attaching one or more die(s) to the lower surface of the substrate, wherein the one or more die(s) extend beyond the upper surface;
overmolding the one or more die(s) and the solder spheres; and
forming through mold vias to expose the solder spheres.

2. The method of claim 1 , wherein forming a substrate with a cavity comprises:
combining layers of prepreg and copper;
removing a cuboid portion of prepreg that extends from the upper surface of the substrate to a copper layer; and
curing the prepreg.

3. The method of claim 2 , wherein removing a cuboid portion of prepreg comprises laser release.

4. The method of claim 1 , wherein attaching one or more die(s) comprises:
coupling a first integrated circuit die to contacts on the lower surface; and
coupling a second integrated circuit die to a surface of the first integrated circuit die.

5. The method of claim 1 , further comprising attaching a device to the solder spheres on the upper surface of the substrate, wherein the device spans the cavity.

6. The method of claim 5 , wherein the device comprises a memory device.

7. The method of claim 1 , wherein attaching one or more die(s) comprises coupling contacts of an integrated circuit die with through silicon vias.

Assignees

• Intel Corp

Inventors

• Modi Mitul
• Sankman Robert L
• Mallik Debendra
• Mahajan Ravindranath V
• Alur Amruthavalli P
• Deng Yikang
• Li Eric J

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title