Ultra-thin, hyper-density semiconductor packages

Patent metadata

Field	Value
Publication number	US-12476174-B2
Application number	US-202318375133-A
Country	US
Kind code	B2
Filing date	Sep 29, 2023
Priority date	Dec 30, 2017
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

First claim

What is claimed is:

1 . A semiconductor assembly, comprising:
a package comprising a first die laterally spaced apart from a second die by a first mold compound, and one or more metal layers and dielectric layers beneath the first die and the second die and the first mold compound; an interposer, wherein the one or more metal layers and dielectric layers of the package are coupled to the interposer by first interconnects; a component beneath the interposer, wherein a top surface of the component is vertically spaced apart from a bottommost surface of the interposer; pillars adjacent to the component and beneath the interposer; a substrate beneath the component and the pillars, the component coupled to the substrate by second interconnects; a second mold compound in contact with sidewalls of the component and extending above the top surface of the component, wherein the second mold compound has an uppermost surface below and in contact with the bottommost surface of the interposer; and solder bumps coupled to the substrate, first ones of the solder bumps vertically beneath the component, and second ones of the solder bumps vertically beneath the pillars.

2 . The semiconductor assembly of claim 1 , wherein the substrate is an ultra-thin substrate.

3 . The semiconductor assembly of claim 1 , wherein the substrate has a thickness in a range of 66 microns to 70 microns.

4 . The semiconductor assembly of claim 1 , wherein the interposer is a pitch translation interposer.

5 . The semiconductor assembly of claim 1 , further comprising:
an epoxy material on a top surface of the component.

6 . The semiconductor assembly of claim 1 , further comprising:
an epoxy layer beneath the component and laterally surrounding the second interconnects.

7 . The semiconductor assembly of claim 1 , wherein the first mold compound has an uppermost surface above an uppermost surface of the first die and the second die.

8 . A semiconductor assembly, comprising:
a first die laterally spaced apart from a second die by a first mold compound; one or more metal layers and dielectric layers beneath the first die and the second die and the first mold compound; an interposer, wherein the one or more metal layers and dielectric layers are coupled to the interposer by first interconnects; a system-on-chip (SoC) beneath the interposer, wherein a top surface of the SoC is vertically spaced apart from a bottommost surface of the interposer; conductive copper structures adjacent to the SoC and beneath the interposer; a substrate beneath the SoC and the conductive copper structures, the SoC coupled to the substrate by second interconnects; a second mold compound in contact with sidewalls of the SoC and extending above the top surface of the SoC, wherein the second mold compound has an uppermost surface below and in contact with the bottommost surface of the interposer; and solder structures coupled to the substrate, first ones of the solder structures vertically beneath the SoC, and second ones of the solder structures vertically beneath the conductive copper structures.

9 . The semiconductor assembly of claim 8 , wherein the substrate is an ultra-thin substrate.

10 . The semiconductor assembly of claim 8 , wherein the substrate has a thickness in a range of 66 microns to 70 microns.

11 . The semiconductor assembly of claim 8 , wherein the interposer is a pitch translation interposer.

12 . The semiconductor assembly of claim 8 , further comprising an epoxy material on a top surface of the SoC.

13 . The semiconductor assembly of claim 8 , further comprising:
an epoxy layer beneath the component and laterally surrounding the second interconnects.

14 . The semiconductor assembly of claim 8 , wherein the first mold compound has an uppermost surface above an uppermost surface of the first die and the second die.

15 . An electronic system, comprising:
one or more system busses; a memory device coupled to the one or more system busses; and a semiconductor assembly coupled to the one or more system busses, the semiconductor assembly comprising:
a package comprising a first die laterally spaced apart from a second die by a first mold compound, and one or more metal layers and dielectric layers beneath the first die and the second die and the first mold compound;
an interposer, wherein the one or more metal layers and dielectric layers of the package are coupled to the interposer by first interconnects;
a component beneath the interposer, wherein a top surface of the component is vertically spaced apart from a bottommost surface of the interposer;
pillars adjacent to the component and beneath the interposer;
a substrate beneath the component and the pillars, the component coupled to the substrate by second interconnects;
a second mold compound in contact with sidewalls of the component and extending above the top surface of the component, wherein the second mold compound has an uppermost surface below and in contact with the bottommost surface of the interposer; and
solder bumps coupled to the substrate, first ones of the solder bumps vertically beneath the component, and second ones of the solder bumps vertically beneath the pillars.

16 . The electronic system of claim 15 , further comprising:
a passive device coupled to the one or more system busses.

17 . The electronic system of claim 15 , further comprising:
a display device coupled to the one or more system busses.

18 . The electronic system of claim 15 , further comprising:
an audio device coupled to the one or more system busses.

19 . The electronic system of claim 15 , further comprising:
a voltage source coupled to the one or more system busses.

20 . The electronic system of claim 15 , further comprising:
a processor coupled to the one or more system busses.

Assignees

• Intel Corp

Inventors

• Mallik Debendra
• Sankman Robert L
• Nickerson Robert
• Modi Mitul
• Ganesan Sanka
• Swaminathan Rajasekaran
• Karhade Omkar
• Liff Shawna M
• Alur Amruthavalli
• Chavali Sri Chaitra J

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title