Section yielding in stacked memory architectures
US-2025336729-A1 · Oct 30, 2025 · US
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Marquart Todd A patents
Marquart Todd A is listed as an inventor on 43 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Marquart Todd A |
| Total patents | 43 |
| First publication | Nov 21, 2019 |
| Latest publication | Oct 30, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Parity data in dynamic random access memory (dram)
US-2024403160-A1 · Dec 5, 2024 · US
Memory sub-system event log management
US-12118229-B2 · Oct 15, 2024 · US
Parity data in dynamic random access memory (DRAM)
US-12061518-B2 · Aug 13, 2024 · US
Partitioned memory having error detection capability
US-12026052-B2 · Jul 2, 2024 · US
Separate partition for buffer and snapshot memory
US-11789629-B2 · Oct 17, 2023 · US
Partitions within snapshot memory for buffer and snapshot memory
US-11775208-B2 · Oct 3, 2023 · US
Threshold voltage based on program/erase cycles
US-11776629-B2 · Oct 3, 2023 · US
Read voltage calibration for copyback operation
US-11694763-B2 · Jul 4, 2023 · US
Parity data in dynamic random access memory (dram)
US-2023185660-A1 · Jun 15, 2023 · US
Recent patents
Latest publications not already listed above.
Threshold voltage distribution adjustment for buffer
US-11663104-B2 · May 30, 2023 · US
Parity data in dynamic random access memory (DRAM)
US-11579964-B2 · Feb 14, 2023 · US
Partitioned memory having error detection capability
US-2023044883-A1 · Feb 9, 2023 · US
Memory sub-system event log management
US-2023017942-A1 · Jan 19, 2023 · US
Data management during a copyback operation
US-11556267-B2 · Jan 17, 2023 · US
Separate partition for buffer and snapshot memory
US-2022350517-A1 · Nov 3, 2022 · US
Trims corresponding to logical unit quantity
US-11487436-B2 · Nov 1, 2022 · US
Partitioned memory having error detection capability
US-11481273-B2 · Oct 25, 2022 · US
Memory sub-system event log management
US-11449266-B2 · Sep 20, 2022 · US
Partitions within snapshot memory for buffer and snapshot memory
US-2022291865-A1 · Sep 15, 2022 · US
Trims corresponding to program/erase cycles
US-11437111-B2 · Sep 6, 2022 · US
Separate partition for buffer and snapshot memory
US-11385819-B2 · Jul 12, 2022 · US
Read voltage calibration for copyback operation
US-2022215895-A1 · Jul 7, 2022 · US
Threshold voltage distribtution adjustment for buffer
US-2022197771-A1 · Jun 23, 2022 · US
Parity data in dynamic random access memory (dram)
US-2022197737-A1 · Jun 23, 2022 · US
Trims corresponding to program/erase cycles
US-2022189571-A1 · Jun 16, 2022 · US
Partitions within snapshot memory for buffer and snapshot memory
US-11360700-B2 · Jun 14, 2022 · US
Read voltage calibration for copyback operation
US-11309052-B2 · Apr 19, 2022 · US
Separate trims for buffer and snapshot
US-11301346-B2 · Apr 12, 2022 · US
Threshold voltage distribution adjustment for buffer
US-11288160-B2 · Mar 29, 2022 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 42 |
| Lodestar Licensing Group Llc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F3/0679 | 21 |
| G06F3/0673 | 18 |
| G06F3/0619 | 15 |
| G06F3/0653 | 14 |
| G06F11/1048 | 13 |