Read voltage calibration for copyback operation

Patent metadata

Field	Value
Publication number	US-11309052-B2
Application number	US-202017001723-A
Country	US
Kind code	B2
Filing date	Aug 25, 2020
Priority date	Aug 25, 2020
Publication date	Apr 19, 2022
Grant date	Apr 19, 2022

Abstract

A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

First claim

What is claimed is:

1. A system, comprising:
a memory device comprising a plurality of groups of memory cells; and
a processing device communicatively coupled to the memory device, wherein the processing device is configured to:
read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the first group of memory cells;
determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality;
prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells:
determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

2. The system of claim 1 , wherein:
the plurality of groups of memory cells corresponds to a first superblock and the memory device further comprises a second superblock;
wherein the processing device is configured to:
perform, to obtain a calibrated read voltage to be used with the second superblock, a read voltage calibration for the second superblock independently from the read voltage calibration performed on the first superblock; and
determine whether to perform a subsequent read voltage calibration on at least a portion of the second superblock based on a BER obtained from applying the calibrated read voltage on the portion of the second superblock.

3. The system of claim 1 , wherein:
the plurality of groups of memory cells corresponds to a first superblock and the memory device further comprises a second superblock; and
the processing device is configured to:
perform a number of read voltage calibrations on the first superblock;
in response to a determination that voltages levels corresponding to the number of read voltage calibrations do not vary by a particular amount, perform a first number of read voltage calibrations on the second superblock; and
in response to a determination that voltages levels corresponding to the number of read voltage calibrations vary by more than a particular amount, perform a second number of read voltage calibrations on the second superblock, wherein the second number of read voltage calibrations is greater in quantity than the first number of read voltage calibrations.

4. The system of claim 1 , wherein the processing device is configured to:
in response to the determined BER being below the threshold BER, skip performance of the subsequent read voltage calibration on the at least second group of the plurality; and
in response to the determined BER being above the threshold BER, perform the subsequent read voltage calibration.

5. The system of claim 1 , wherein:
the plurality of groups of memory cells corresponds to a block of NAND memory cells;
the first group of memory cells corresponds to a first sample page of the block of NAND memory cells; and
the second group of memory cells corresponds to a second sample page of the block of NAND memory cells;
wherein the processing device is configured to determine whether to perform the subsequent read voltage calibration on the second sample page of the block of NAND memory cells based, at least partially, on a comparison on between the determined BER of the first sample page and the threshold BER.

6. The system of claim 1 , wherein the processing device is configured to cause the memory device to perform the copyback operation on data stored in the first group of memory cells using the calibrated read voltage associated with the first group to copy the data from the plurality of groups of memory cells to a different plurality of groups of memory cells.

7. The system of claim 1 , wherein:
the memory device comprises a plurality of NAND dies; and
memory cells of the plurality of groups of memory cells are distributed over multiple dies of the plurality of NAND dies.

8. A method, comprising:
in response to a trigger event, receiving a request to copy data stored in a first plurality of groups of memory cells of a cyclic buffer portion of a memory device to a second plurality of groups of memory cells of a snapshot portion of the memory device;
prior to copying the data from the first plurality of groups of memory cells to the second plurality of groups of memory cells via a copyback operation:
determining a calibrated read voltage by performing a read voltage calibration on a first sample group of the first plurality of groups by adjusting a read voltage used to read the first sample group;
determining a bit error rate (BER) of a second sample group of the first plurality of groups using the calibrated read voltage; and
responsive to the determined BER of the second sample group being below a threshold BER, performing the copyback operation on the first plurality of groups of memory cells to copy the data from the first plurality of groups to the second plurality of groups.

9. The method of claim 8 , wherein performing the copyback operation on the first plurality of groups of memory cells further comprises:
determining data values stored in the first plurality of groups of memory cells by reading at least one group of the first plurality of groups of memory cells using the calibrated read voltage; and
writing the determined data values to the second plurality of groups of memory cells of the snapshot portion.

10. The method of claim 8 , further comprising, responsive to the determined BER being above the threshold BER:
performing a subsequent read voltage calibration on at least the second sample group of the first plurality of groups to determine an additional calibrated read voltage by adjusting the read voltage to a third voltage level; and
performing the copyback operation on:
the first sample page of the first plurality using the calibrated read voltage; and
the at least the second sample group of the first plurality using the additional calibrated read voltage.

11. The method of claim 8 , wherein performing the read voltage calibration on the first sample group further comprises:
reading the first sample group using a plurality of read voltages, wherein a plurality of respective BERs is obtained responsive to using the plurality of read voltages; and
determining a voltage level of the calibrated read voltage based on the plurality of obtained BERs.

12. The method of claim 8 , further comprising:
operating memory cells of the first plurality of the cyclic buffer portion in a single-level cell (SLC) mode; and
operating memory cells of the second plurality of the snapshot portion in a multiple level cell mode.

13. A system, comprising:
a processing device;
trigger circuitry to signal the processing device responsive to occurrence of a trigger event; and
a memory device coupled to the processing device and comprising:
a cyclic buffer portion comprising a plurality of blocks of NAND memory cells; and
a snapshot portion; and

wherein the processing device is configured to, in response to occurrence of the trigger event:
determine that a particular block of the plurality of blocks of the cyclic buffer portion comprises time based telemetric sensor data to be copied to a snapshot portion;
perform a read voltage calibration on a first sample page of the particular block to determine a calibrated a read voltage;
use the calibrated read voltage to determine a bit error rate (BER) of a number of additional sample pages of the particular block;
in response to the determined BER of the number of additional sample pages being below a threshold BER, perform a copyback ope

Assignees

• Micron Technology Inc

Inventors

• Muchherla Kishore K
• Righetti Niccolo'
• Mcneil Jr Jeffrey S
• Goda Akira
• Marquart Todd A
• Helm Mark A
• Golov Gil
• Binfet Jeremy
• Miccoli Carmine
• Puzzilli Giuseppina

Classifications

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/021 Primary

  in voltage or current generators · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title