Trims corresponding to program/erase cycles

Patent metadata

Field	Value
Publication number	US-11437111-B2
Application number	US-202017122758-A
Country	US
Kind code	B2
Filing date	Dec 15, 2020
Priority date	Dec 15, 2020
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

Instructions can be executed to adjust a trim at first intervals until a quantity of program/erase cycles (PEC) have occurred. The trim defines a valley width between data states. Instructions can be executed to adjust the trim at second intervals, greater than the first intervals, after the quantity of PEC have occurred.

First claim

What is claimed is:

1. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
adjust a trim at first intervals until a quantity of program/erase cycles (PEC) have occurred, wherein the trim defines a valley width between data states; and
adjust the trim at second intervals, greater than the first intervals, after the quantity of PEC have occurred.

2. The medium of claim 1 , wherein each of the first intervals comprises a first quantity of PEC; and
wherein each of the second intervals comprises a second quantity of PEC greater than the first quantity of PEC.

3. The medium of claim 1 , further comprising instructions to:
adjust the trim by a first step at the first intervals; and
adjust the trim by a second step, larger than the first step, at the second intervals.

4. The medium of claim 3 , wherein the instructions to adjust the trim comprise instructions to define a program verify voltage and an erase verify voltage;
wherein the first step comprises an increase in a difference between the program verify voltage and the erase verify voltage of a first magnitude; and
wherein the second step comprises an increase in the difference between the program verify voltage and the erase verify voltage of a second magnitude, greater than the first magnitude.

5. The medium of claim 1 , wherein the instructions to adjust the trim comprise instructions to define a program verify voltage for programming memory cells to a programmed state.

6. The medium of claim 5 , wherein the instructions to adjust the trim further comprise instructions to define an erase verify voltage for erasing memory cells.

7. The medium of claim 1 , wherein the quantity of PEC comprises a first quantity of PEC; and
further comprising instructions to:
adjust the trim at second intervals until a second quantity of PEC have occurred; and
adjust the trim at third intervals, greater than the second intervals, after the second quantity of PEC have occurred.

8. The medium of claim 7 , further comprising instructions to:
wear level blocks of memory according to a first wear leveling algorithm until a third quantity of PEC have occurred;
wherein the third quantity of PEC is greater than the first quantity of PEC and less than the second quantity of PEC;
wear level the blocks of memory according to a second wear leveling algorithm until a fourth quantity of PEC have occurred;
wherein the fourth quantity of PEC is greater than the second quantity of PEC.

9. A system comprising:
a memory device; and
a processing device coupled to the memory device, wherein the processing device is to:
adjust a trim defining a program verify voltage corresponding to a data state at a first frequency relative to a quantity of program/erase cycles (PEC) during an early portion of a life of a memory device;
adjust the trim defining the program verify voltage corresponding to the data state at a second frequency, less than the first frequency, relative to the quantity of PEC during a middle portion of the life of the memory device; and
adjust the trim defining the program verify voltage corresponding to the data state at a third frequency, less than the second frequency, relative to the quantity of PEC during a late portion of the life of the memory device.

10. The system of claim 9 , wherein the first frequency, the second frequency, and the third frequency comprise PEC frequencies.

11. The system of claim 10 , wherein the quantity of PEC is the quantity of PEC that the memory device has undergone at a given point in time.

12. The system of claim 10 , wherein the quantity of PEC is the quantity of PEC that a block including a memory cell to be programmed has undergone at a time at which it is to be programmed.

13. The system of claim 9 , wherein the processing device is further to:
adjust the trim defining the program verify voltage by a first magnitude at the first frequency during the early portion of the life of the memory device;
adjust the trim defining the program verify voltage by a second magnitude at the second frequency during the middle portion of the life of the memory device; and
adjust the trim defining the program verify voltage by a third magnitude at the third frequency during the late portion of the life of the memory device.

14. The system of claim 13 , wherein the first magnitude is less than the second magnitude; and
wherein the second magnitude is less than the third magnitude.

15. The system of claim 9 , wherein the processing device is further to:
adjust a trim defining an erase verify voltage at the first frequency during the early portion of the life of the memory device;
adjust the trim defining the erase verify voltage at the second frequency during the middle portion of the life of the memory device; and
adjust the trim defining the erase verify voltage at the third frequency during the late portion of the life of the memory device.

16. The system of claim 15 , wherein the processing device is further to:
adjust the trim defining the erase verify voltage by a first magnitude at the first frequency during the early portion of the life of the memory device;
adjust the trim defining the erase verify voltage by a second magnitude at the second frequency during the middle portion of the life of the memory device; and
adjust the trim defining the erase verify voltage by a third magnitude at the third frequency during the late portion of the life of the memory device.

17. The system of claim 16 , wherein the first magnitude is less than the second magnitude; and
wherein the second magnitude is less than the third magnitude.

18. A method, comprising:
receiving a respective indication for each of a plurality of completions of a first interval of program/erase cycles (PEC);
adjusting a trim defining a valley width between data states by a first magnitude in response to the respective indication of the first interval;
subsequently receiving a respective indication for each of a plurality of completions of a second interval of PEC;
wherein the second interval includes more PEC than the first interval; and
adjusting the trim by a second magnitude, greater than the first magnitude, in response to the respective indication of the second interval.

19. The method of claim 18 , further comprising:
programming a first memory cell using the trim adjusted by the first magnitude prior to receiving any indication of completion of the second interval of PEC; and
programming a second memory cell using the trim adjusted by the second magnitude after receiving any indication of completion of the second interval of PEC.

20. The method of claim 18 , further comprising subsequently receiving a respective indication for each of a plurality of completions of a third interval of PEC;
wherein the third interval includes more PEC than the second interval; and
adjusting the trim by a third magnitude, greater than the second magnitude, in response to the respective indication of the third interval.

Assignees

• Micron Technology Inc

Inventors

• Mcneil Jr Jeffrey S
• Schuh Karl D
• Rayaprolu Vamsi Pavan
• Puzzilli Giuseppina
• Muchherla Kishore K
• Golov Gil
• Marquart Todd A
• Wu Jiangang
• Righetti Niccolo'
• Malshe Ashutosh

Classifications

• G11C16/3495 Primary

  Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C16/32

  Timing circuits · CPC title