Parity data in dynamic random access memory (DRAM)

Patent metadata

Field	Value
Publication number	US-12061518-B2
Application number	US-202318108876-A
Country	US
Kind code	B2
Filing date	Feb 13, 2023
Priority date	Dec 22, 2020
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

First claim

What is claimed is:

1. A method, comprising:
receiving user data from a non-volatile memory device at a controller;
receiving parity data corresponding to the user data from a dynamic random access memory (DRAM) device at the controller;
reconstructing the user data in one clock cycle at the controller; and
regenerating the parity data in response to powering off and powering on the DRAM device.

2. The method of claim 1 , further comprising receiving the parity data and reconstructing the user data in response to a read failure.

3. The method of claim 2 , further comprising receiving the parity data and reconstructing the user data in response to the read failure, wherein the read failure is due to corrupted memory in the non-volatile memory device.

4. The method of claim 1 , further comprising reading the user data and reconstructing the user data in one clock cycle.

5. The method of claim 1 , further comprising generating the parity data at the controller by performing an error correction code (ECC) operation on the user data.

6. The method of claim 1 , further comprising performing a RAID operation on the user data to generate the parity data at the controller.

7. An apparatus, comprising:
a dynamic random access memory (DRAM) device;
a non-volatile memory device coupled to the DRAM device, wherein the non-volatile memory device is configured to store user data; and
a controller coupled to the DRAM device and the non-volatile memory device, wherein the controller is configured to:
receive the user data from the non-volatile memory device; and
perform an ECC operation on the user data to regenerate parity data in response to powering on the DRAM device.

8. The apparatus of claim 7 , wherein the controller comprises an error correction code (ECC) module configured to perform the ECC operation.

9. The apparatus of claim 7 , wherein the ECC operation is an XOR operation.

10. The apparatus of claim 7 , wherein the controller is configured to perform the ECC operation in one clock cycle.

11. The apparatus of claim 7 , wherein the controller is configured to rewrite the parity data to the DRAM device in response to powering on the DRAM device.

12. The apparatus of claim 7 , wherein the controller is configured to regenerate the parity data in response to powering off and powering on the DRAM device.

13. The apparatus of claim 7 , wherein the apparatus is a non-volatile dual in-line memory module (NVDIMM).

14. An apparatus, comprising:
a controller configured to generate parity data based on user data;
a dynamic random access memory (DRAM) device configured to store the parity data; and
a non-volatile memory device configured to:
store the user data; and
store the parity data prior to powering off the DRAM device; and

wherein the controller is configured to rewrite the parity data to the DRAM device in response to powering on the DRAM device.

15. The apparatus of claim 14 , wherein the non-volatile memory device is a 3D Cross-point device.

16. The apparatus of claim 14 , wherein the controller is configured to generate the parity data based on the user data in response to receiving a write command.

17. The apparatus of claim 16 , wherein the write command includes the user data.

18. The apparatus of claim 14 , wherein the controller is configured to generate the parity data based on the user data, wherein the user data is queued for writing to the non-volatile memory device.

Assignees

• Micron Technology Inc

Inventors

• Mylavarapu Sai Krishna
• Marquart Todd A

Classifications

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C2029/0411

  Online error correction · CPC title