Memory sub-system event log management

US11449266B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11449266-B2
Application numberUS-202017004135-A
CountryUS
Kind codeB2
Filing dateAug 27, 2020
Priority dateAug 27, 2020
Publication dateSep 20, 2022
Grant dateSep 20, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system includes a memory device and a processing device coupled to the memory device. The memory processing device can perform operations including receiving data indicative of occurrence of a plurality of events. The processing device can perform operations including determining an event log type for each of the plurality of events. The processing device can perform operations including storing an identifier associated with each of the determined event log types. The processing device can perform operations including updating a counter value associated with each identifier in response to occurrence of an event associated with the respective identifier.

First claim

Opening claim text (preview).

What is claimed is: 1. A system, comprising: a memory device; and a processing device coupled to the memory device to control: receiving data indicative of occurrence of a plurality of events; determining an event log type for each of the plurality of events; writing an identifier associated with each of the determined event log types to the memory device; updating a counter value associated with each identifier in response to performance of an event associated with the respective identifier; wherein the size of each of the identifiers is based on: a quantity of the plurality of events; and a size of a memory space for storing each of the identifiers and associated counters. 2. The system of claim 1 , wherein the processing device is configured to determine if the event log type is an error event. 3. The system of claim 1 , wherein the processing device is configured to generate histogram data from the determined event log types and the updated counter value and display the histogram data. 4. The system of claim 1 , wherein the received data comprise a listing of each event occurring during a particular period of time. 5. The system of claim 4 , wherein the processing device is further configured to flush the listing of the events occurring during the particular period of time at particular intervals of time. 6. The system of claim 5 , wherein the processing device configured to perform flush the listing of the events occurring during the particular period of time at one or more of: a clean power cycle; a boot-up; a reboot; and a threshold counter saturation value. 7. A method, comprising: receiving, from a memory device, data indicative of occurrence of a plurality of events; determining an event log type for each of the plurality of events; writing an identifier associated with each of the determined event log types in an event log within the memory device; updating a counter associated with each identifier in the event log in response to occurrence of an event associated with the respective identifier; generating histogram data using the event log types and corresponding identifiers and counter values; and flushing the event log types and corresponding identifiers and counter values to the histogram data based on at least one of the counter values reaching a maximum threshold value. 8. The method of claim 7 , wherein the histogram data further comprises: a plurality of identifiers; and a corresponding plurality of counters indicating a quantity of times each event log type associated with each of the respective plurality of identifiers has occurred. 9. The method of claim 8 , wherein generating the histogram data comprises generating a histogram that indicates the quantity of times each event log type has occurred per period of time. 10. The method of claim 7 , further comprising determining that the event log type comprises an error event. 11. The method of claim 7 , further comprising determining that the event log type comprises one of a non-critical event or a critical event. 12. The method of claim 7 , further comprising storing the counters in a location of memory separate from a location of the identifiers. 13. The method of claim 7 , further comprising determining a priority of the counters and corresponding event log types. 14. A system, comprising: a memory device; and a processing device coupled to the memory device and configured to perform operations comprising: managing an event log corresponding to a plurality of event log types; receiving data indicative of occurrences of the plurality of events; determining an event log type for respective occurrences of the plurality of events; writing an identifier associated with each of the determined event log types in an event log within the memory device; generating histogram data comprising the occurrences of the plurality of events and the event log types; updating a counter of the event histogram associated with each of the identifiers in response to a determined occurrence of an event associated with the respective identifier; and flushing the event log types and each of the corresponding identifiers and counter values during a clean power cycle to a non-volatile memory device. 15. The system of claim 14 , wherein the processing device is configured to determine a bit-size of the counter based on a frequency of the plurality of events occurring and a bit to event ratio. 16. The system of claim 14 , wherein the processing device is configured to determine a bit-size of the counter based on an amount of time that the event log type will be entered into the histogram. 17. The system of claim 14 , wherein the system comprises a solid state drive (SSD). 18. The system of claim 14 , wherein the processing device is configured to perform operations comprising determining the identifier associated with each of the determined event log types. 19. The system of claim 14 , wherein the system comprises a memory sub-system controller comprising the processing device, and wherein the memory sub-system is coupled to a host system via interface circuitry.

Assignees

Inventors

Classifications

  • in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

  • by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

  • Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

  • Single storage device · CPC title

  • Improving I/O performance · CPC title

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What does patent US11449266B2 cover?
A system includes a memory device and a processing device coupled to the memory device. The memory processing device can perform operations including receiving data indicative of occurrence of a plurality of events. The processing device can perform operations including determining an event log type for each of the plurality of events. The processing device can perform operations including stor…
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification G06F11/0727. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 20 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).