System for monitoring and controlling an integrated circuit testing machine
US-11428735-B1 · Aug 30, 2022 · US
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Khandekar Viren patents
Khandekar Viren is listed as an inventor on 20 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Khandekar Viren |
| Total patents | 20 |
| First publication | Jan 8, 2015 |
| Latest publication | Aug 30, 2022 |
Notable patents
Publications ranked by popularity score, then publication date.
Wafer-level chip-scale package device having bump assemblies configured to maintain standoff height
US-10804233-B1 · Oct 13, 2020 · US
Wafer level package device formed using a wafer level lead frame on a carrier wafer having a similar coefficient of thermal expansion as an active wafer
US-10304758-B1 · May 28, 2019 · US
Three-dimensional chip-to-wafer integration
US-10032749-B2 · Jul 24, 2018 · US
Wafer-level chip-scale package device having bump assemblies configured to furnish shock absorber functionality
US-9721912-B2 · Aug 1, 2017 · US
Solder fatigue arrest for wafer level package
US-9583425-B2 · Feb 28, 2017 · US
Technique for wafer-level processing of QFN packages
US-9472451-B2 · Oct 18, 2016 · US
Low-cost low-profile solder bump process for enabling ultra-thin wafer-level packaging (WLP) packages
US-9425064-B2 · Aug 23, 2016 · US
Wafer-level passive device integration
US-9324687-B1 · Apr 26, 2016 · US
Three-dimensional chip-to-wafer integration
US-2016071826-A1 · Mar 10, 2016 · US
Recent patents
Latest publications not already listed above.
Multi-die, high current wafer level package
US-9230903-B2 · Jan 5, 2016 · US
Wafer-level package device having high-standoff peripheral solder bumps
US-9219043-B2 · Dec 22, 2015 · US
Three-dimensional chip-to-wafer integration
US-9190391-B2 · Nov 17, 2015 · US
Multi-die, high current wafer level package
US-2015325512-A1 · Nov 12, 2015 · US
Integrated circuit device having extended under ball metallization
US-9093333-B1 · Jul 28, 2015 · US
Multi-die, high current wafer level package
US-9087779-B2 · Jul 21, 2015 · US
Wafer-level package device having solder bump assemblies that include an inner pillar structure
US-9087732-B1 · Jul 21, 2015 · US
Techniques for wafer-level processing of QFN packages
US-9040408-B1 · May 26, 2015 · US
Technique for wafer-level processing of qfn packages
US-2015028475-A1 · Jan 29, 2015 · US
Wafer-level chip-scale package device having bump assemblies configured to furnish shock absorber functionality
US-2015008576-A1 · Jan 8, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Maxim Integrated Products | 20 |
| Thambidurai Karthik | 2 |
| Khandekar Viren | 2 |
| Kelkar Amit Subhash | 1 |
| Nguyen Hien D | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W72/0198 | 17 |
| H10W72/252 | 16 |
| H10W72/29 | 13 |
| H10W90/722 | 11 |
| H10W90/724 | 10 |