Three-dimensional chip-to-wafer integration

Patent metadata

Field	Value
Publication number	US-2016071826-A1
Application number	US-201514942708-A
Country	US
Kind code	A1
Filing date	Nov 16, 2015
Priority date	Oct 26, 2011
Publication date	Mar 10, 2016
Grant date	—

Abstract

An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold.

First claim

1 . A semiconductor device comprising:
a semiconductor substrate; a die attached to the semiconductor substrate; an overmold molded onto the semiconductor substrate over the die; and a conductive pillar connected to at least one of the semiconductor substrate or the die, the conductive pillar extending through the overmold.

2 . The semiconductor device as recited in claim 1 , wherein the semiconductor substrate and the die comprise at least substantially the same coefficient of thermal expansion.

3 . The semiconductor device as recited in claim 1 , wherein the semiconductor substrate comprises a carrier, and the connections to the die fan-out.

4 . The semiconductor device as recited in claim 1 , wherein the semiconductor substrate comprises a second die.

5 . The semiconductor device as recited in claim 4 , wherein the die comprises one of an analog component or a digital component and the second die comprises the other of an analog component or a digital component.

6 . The semiconductor device as recited in claim 1 , further comprising:
a redistribution layer formed on the overmold; and a plurality of solder bumps formed on the redistribution layer, at least one of the plurality of solder bumps connected to the conductive pillar via the redistribution layer.

7 . The semiconductor device as recited in claim 1 , wherein the die is attached to the semiconductor substrate in a face-up orientation.

8 . (canceled)

9 . The semiconductor device as recited in claim 1 , wherein the conductive pillar furnishes electrical connection to the at least one of the semiconductor substrate or the die.

10 . The semiconductor device as recited in claim 1 , wherein the conductive pillar is configured to transfer heat from at least one of the semiconductor substrate or the die.

11 . The semiconductor device as recited in claim 1 , further comprising a heat sink coupled with a side of the semiconductor substrate opposite the die.

12 . A method of fabricating a wafer level package comprising:
placing a die on a semiconductor substrate; forming a conductive pillar on at least one of the die or the semiconductor substrate, the conductive pillar connected to the at least one of the semiconductor substrate or the die; and molding an overmold onto the semiconductor substrate over the die, the conductive pillar extending through the overmold.

13 . The method as recited in claim 12 , further comprising:
forming a redistribution layer on the overmold; and forming a plurality of solder bumps on the redistribution layer, at least one of the plurality of solder bumps connected to the conductive pillar via the redistribution layer.

14 . The method as recited in claim 12 , wherein the semiconductor substrate and the die comprise at least substantially the same coefficient of thermal expansion.

15 . The method as recited in claim 12 , wherein placing a die on a semiconductor substrate comprises placing the die on the semiconductor substrate in a face-up orientation.

16 . The method as recited in claim 12 , wherein placing a die on a semiconductor substrate comprises placing the die on the semiconductor substrate in a face-down orientation.

17 . The method as recited in claim 12 , wherein the conductive pillar furnishes electrical connection to the at least one of the semiconductor substrate or the die.

18 . The method as recited in claim 12 , wherein the conductive pillar is configured to transfer heat from at least one of the semiconductor substrate or the die.

19 . A semiconductor device comprising:
a first die; a second die attached to the first die; an overmold molded onto the first die over the second die; and a conductive pillar connected to at least one of the first die or the second die, the conductive pillar extending through the overmold.

20 . The wafer level package as recited in claim 19 , wherein the first die and the second die comprise at least substantially the same coefficient of thermal expansion.

Assignees

• Maxim Integrated Products

Inventors

• Kelkar Amit S
• Thambidurai Karthik
• Khandekar Viren
• Nguyen Hien D

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title