Multi-die, high current wafer level package

Patent metadata

Field	Value
Publication number	US-9230903-B2
Application number	US-201514803612-A
Country	US
Kind code	B2
Filing date	Jul 20, 2015
Priority date	Jan 2, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts.

First claim

What is claimed is:

1. A process comprising:
forming a pillar upon a semiconductor wafer, the pillar extending from the semiconductor wafer to a first height above the semiconductor wafer;
connecting an integrated circuit chip device to the semiconductor wafer, the integrated circuit chip device extending from the semiconductor wafer to a second height above the semiconductor wafer;
forming an encapsulation structure over the semiconductor wafer, the encapsulation structure at least substantially encapsulating the pillar; and
applying at least one solder contact to the pillar, the at least one solder contact being located at a third height above the semiconductor wafer,
wherein the second height is less than at least one of: the first height and the third height;
wherein the step of forming the pillar upon the semiconductor wafer comprises:
depositing a blanket seed layer on the semiconductor wafer;
applying a first photoresist layer over the semiconductor wafer;
patterning and etching the first photoresist layer to form an etched area;
depositing a conductive material in the etched area to form a first layer of the pillar;
at least substantially removing the first photoresist layer;
applying a second photoresist layer over the semiconductor wafer;
patterning and etching the second photoresist layer to form an etched area of the second photoresist layer;
depositing conductive material in the etched area of the second photoresist layer to form a second layer of the pillar;
at least substantially removing the second photoresist layer; and
etching the blanket seed layer.

2. The process as claimed in claim 1 , wherein forming the encapsulation structure further comprises depositing an epoxy material over the semiconductor wafer, the encapsulation structure at least partially encapsulating the pillar and the integrated circuit chip device.

3. The process as claimed in claim 1 , wherein the step of connecting the integrated circuit chip device to the semiconductor wafer further comprises:
applying an underfill to the integrated circuit chip device.

4. The process as claimed in claim 1 , further comprising:
prior to applying the at least one solder contact to the pillar, grinding the encapsulation structure to expose the pillar.

Assignees

• Maxim Integrated Products

Inventors

• Samoilov Arkadii V
• Harper Peter R
• Khandekar Viren
• Parvarandeh Pirooz

Classifications

• H10W72/0198

  batch processes · CPC title

• H10P50/28

  of insulating materials · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title