Wafer level package device formed using a wafer level lead frame on a carrier wafer having a similar coefficient of thermal expansion as an active wafer

Patent metadata

Field	Value
Publication number	US-10304758-B1
Application number	US-201313788291-A
Country	US
Kind code	B1
Filing date	Mar 7, 2013
Priority date	Mar 7, 2013
Publication date	May 28, 2019
Grant date	May 28, 2019

Abstract

Techniques for forming a wafer level package device are disclosed. In one or more embodiments, the techniques include forming a wafer level lead frame on a carrier wafer and electrically connecting the wafer level lead frame to an active semiconductor wafer. The carrier wafer and the active semiconductor wafer have at least substantially the same coefficients of thermal expansion. The carrier wafer can be removed from the wafer level package device, and a number of connectors can be formed on the wafer level package device. The wafer level package device can be singulated to form chip packages, such as DFN or QFN packages.

First claim

What is claimed is:

1. A wafer level package device comprising:
a wafer level lead frame formed on a first substrate, the the first substrate configured to be attached to a removable non-metal carrier wafer comprising at least one of a semiconductor or an insulator, the removable non-metal carrier wafer having a first coefficient of thermal expansion, the removable non-metal carrier wafer having one or more apertures configured to receive an epoxy molding material; and
a second substrate formed from an active semiconductor wafer, the second substrate electrically and mechanically connected to the wafer level lead frame by a plurality of solder bumps, the active semiconductor wafer having a second coefficient of thermal expansion at least substantially similar to the first coefficient of thermal expansion, where the epoxy molding material is compression molded in a space between the wafer level lead frame and the second substrate about the plurality of solder bumps via the one or more apertures in the non-metal carrier wafer;
the wafer level lead frame comprising a plurality of connectors that are configured to be exposed after the removable non-metal carrier wafer has been removed to furnish electrical connectivity to the second substrate, wherein the epoxy molding material is disposed below the plurality of connectors.

2. The wafer level package device as recited in claim 1 , wherein the removable non-metal carrier wafer is configured to be removed from the wafer level package device.

3. The wafer level package device as recited in claim 1 , wherein the wafer level package device is configured to be singulated to form a plurality of chip packages.

4. The wafer level package device as recited in claim 1 , wherein at least one of the plurality of connectors formed on the wafer level package device comprises electroless nickel immersion gold (ENIG) plating.

5. The wafer level package device as recited in claim 1 , wherein the removable non-metal carrier wafer comprises at least one aperture for receiving the epoxy molding material.

Assignees

• Maxim Integrated Products

Inventors

• Thambidurai Karthik
• Ashrafzadeh Ahmad
• Patel Viresh P
• Khandekar Viren

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07207

  Temporary substrates, e.g. removable substrates · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title