Multi-die, high current wafer level package

Patent metadata

Field	Value
Publication number	US-9087779-B2
Application number	US-201313732664-A
Country	US
Kind code	B2
Filing date	Jan 2, 2013
Priority date	Jan 2, 2013
Publication date	Jul 21, 2015
Grant date	Jul 21, 2015

Abstract

Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts.

First claim

What is claimed is:

1. A wafer-level package device comprising:
an integrated circuit chip having a surface;
a pillar extending from the surface of the integrated circuit chip, the pillar having an end distal from the surface of the integrated circuit chip, the distal end of the pillar being located at a first height above the surface of the integrated circuit chip, the pillar configured to provide an electrical interconnection to the integrated circuit chip;
an integrated circuit chip device, the integrated circuit chip device being configured upon the surface of the integrated circuit chip, the integrated circuit chip device having a surface distal from the surface of the integrated circuit chip, the distal surface of the integrated circuit chip device being located at a second height above the surface of the integrated circuit chip;
a first solder contact and a second solder contact disposed upon the distal end of the pillar through a first solder mask opening and a second solder mask opening, respectively, the first and second solder contacts being located at a third height above the surface of the integrated circuit chip; and
an encapsulation structure disposed over the surface of the integrated circuit chip, the encapsulation structure enclosing the pillar except for portions of the pillar underlying the first solder mask opening and the second solder mask opening,
wherein the second height is less than at least one of: the first height and the third height.

2. The wafer-level package device as claimed in claim 1 , wherein the pillar comprises a copper pillar.

3. The wafer-level package device as claimed in claim 1 , further comprising an underfill between the integrated circuit chip device and the integrated circuit chip.

4. The wafer-level package device as claimed in claim 1 , wherein the encapsulation structure at least partially encloses the integrated circuit chip device.

5. A wafer-level package device comprising:
an integrated circuit chip having a surface;
a pillar extending from the surface of the integrated circuit chip, the pillar having an end distal from the surface, the pillar configured to provide an electrical interconnection to the integrated circuit chip;
a first solder contact and a second solder contact disposed upon the distal end of the pillar in a first solder area and a second solder area, respectively;
an integrated circuit chip device, the integrated circuit chip device being configured upon the surface of the integrated circuit chip, the integrated circuit chip device having a surface distal from the surface of the integrated circuit chip; and
an encapsulation structure disposed over the surface of the integrated circuit chip, the encapsulation structure at least partially enclosing the pillar, the encapsulation structure defining the first solder area and the second solder area, the first solder area being separated from the second solder area by the encapsulation structure.

6. The wafer-level package device as claimed in claim 5 , wherein the distal end of the pillar is located a first distance above the surface of the integrated circuit chip, while the distal surface of the integrated circuit chip device is located a second distance above the surface of the integrated circuit chip, the first distance being greater than the second distance.

7. The wafer-level package device as claimed in claim 5 , wherein the first and second solder contacts are located a first distance above the surface of the integrated circuit chip, while the distal surface of the integrated circuit chip device is located a second distance above the surface of the integrated circuit chip, the first distance being greater than the second distance.

8. The wafer-level package device as claimed in claim 5 , wherein the pillar comprises a copper pillar.

9. The wafer-level package device as claimed in claim 5 , wherein the encapsulation structure comprises an epoxy material.

10. The wafer-level package device as claimed in claim 5 , further comprising an underfill between the integrated circuit chip device and the integrated circuit chip.

11. The wafer-level package device as claimed in claim 5 , wherein the encapsulation structure at least partially encloses the integrated circuit chip device.

Assignees

• Maxim Integrated Products

Inventors

• Samoilov Arkadii V
• Harper Peter R
• Khandekar Viren
• Parvarandeh Pirooz

Classifications

• H10W72/0198

  batch processes · CPC title

• H10P50/28

  of insulating materials · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title