Technique for wafer-level processing of QFN packages

Patent metadata

Field	Value
Publication number	US-9472451-B2
Application number	US-201414512506-A
Country	US
Kind code	B2
Filing date	Oct 13, 2014
Priority date	Dec 27, 2011
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

First claim

What is claimed is:

1. A wafer-level package device comprising:
an integrated circuit chip having a surface;
a plurality of pillars extending from the surface, the plurality of pillars having an end distal from the surface, the plurality of pillars configured to provide an electrical interconnection to the integrated circuit chip;
a first photoresist layer disposed over the surface; and
a second photoresist layer disposed over the first photoresist layer,
wherein a first pillar of the plurality of pillars extends through the first photoresist layer and the second photoresist layer and a second pillar of the plurality of pillars extends only through the first photoresist layer.

2. The wafer-level package device as recited in claim 1 , wherein the plurality of pillars comprise copper pillars.

3. The wafer-level package device as recited in claim 1 , wherein the aspect ratio of the plurality of pillars ranges from at least approximately one to one (1:1) to at least approximately twenty to one (20:1).

4. The wafer-level package device as recited in claim 1 , wherein the aspect ratio of the plurality of pillars ranges from at least approximately five to one (5:1) to at least approximately fifteen to one (15:1).

5. A semiconductor device comprising:
an integrated circuit chip having a surface;
a plurality of pillars extending from the surface, the plurality of pillars having an end distal from the surface, the plurality of pillars configured to provide an electrical interconnection to the integrated circuit chip;
a first photoresist layer disposed over the surface; and
a second photoresist layer disposed over the first photoresist layer,
wherein a first pillar of the plurality of pillars extends through the first photoresist layer and the second photoresist layer and a second pillar of the plurality of pillars extends only through the first photoresist layer, wherein the aspect ratio of the plurality of pillars ranges from at least approximately one to one (1:1) to at least approximately twenty to one (20:1).

6. The semiconductor device as recited in claim 5 , wherein the plurality of pillars comprise copper pillars.

7. The semiconductor device as recited in claim 5 , wherein the aspect ratio of the plurality of pillars from at least approximately five to one (5:1) to at least approximately fifteen to one (15:1).

Assignees

• Maxim Integrated Products

Inventors

• Khandekar Viren
• Thambidurai Karthik
• Ashrafzadeh Ahmad
• Kelkar Amit S
• Nguyen Hien D

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W74/014

  using batch processing · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9223

  with redistribution layers [RDL] · CPC title

• H10W72/01955

  by using masks · CPC title