Three-dimensional chip-to-wafer integration

Patent metadata

Field	Value
Publication number	US-10032749-B2
Application number	US-201514942708-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Oct 26, 2011
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate, the semiconductor substrate having electrical circuitry, the semiconductor substrate further having a plurality of solder balls attached thereto;
a first die having a first face, a second face, and a die attach pad disposed in the first face, the solder balls further attached to the second face;
a second die having a second face, the second die attached to the die attach pad disposed in the first face of the first die, the first die and the second die stacked so that the first face and the second face are in direct contact;
an overmold molded onto the semiconductor substrate over the first die and the second die;
a conductive pillar connected to at least one of the electrical circuitry of the semiconductor substrate, the first die, or the second die, the conductive pillar extending through the overmold;
a redistribution layer formed on the overmold; and
a plurality of solder bumps formed on the redistribution layer, at least one of the plurality of solder bumps connected to the conductive pillar via the redistribution layer.

2. The semiconductor device as recited in claim 1 , wherein the semiconductor substrate and the first die comprise at least substantially the same coefficient of thermal expansion.

3. The semiconductor device as recited in claim 1 , wherein the semiconductor substrate comprises a carrier, and a plurality of connections to a first die fan-out.

4. The semiconductor device as recited in claim 1 , wherein the semiconductor substrate comprises a third die.

5. The semiconductor device as recited in claim 4 , wherein the first die comprises one of an analog component or a digital component and the semiconductor substrate comprises the other of an analog component or a digital component.

6. The semiconductor device as recited in claim 1 , wherein the conductive pillar furnishes electrical connection to the at least one of the semiconductor substrate or the second die.

7. The semiconductor device as recited in claim 1 , wherein the conductive pillar is configured to transfer heat from at least one of the semiconductor substrate or the second die.

8. The semiconductor device as recited in claim 1 , further comprising a heat sink coupled with a side of the semiconductor substrate opposite the second die.

9. A semiconductor device comprising:
a first die, the first die having electrical circuitry;
a second die attached to the first die, the second die having a first face and a die attach pad disposed in the first face;
a third die having a second face, the third die attached to the die attach pad disposed in the first face of the second die, the second die and the third die stacked so that the first face and the second face are in direct contact;
an overmold molded onto the first die over the second die;
a conductive pillar connected to at least one of the electrical circuitry of the first die, the second die, or the third die, the conductive pillar extending through the overmold;
a redistribution layer formed on the overmold; and
a plurality of solder bumps formed on the redistribution layer, at least one of the plurality of solder bumps connected to the conductive pillar via the redistribution layer.

10. The semiconductor device as recited in claim 9 , wherein the first die and the second die comprise at least substantially the same coefficient of thermal expansion.

11. The semiconductor device as recited in claim 1 , wherein the second face of the first die is positioned in substantially facing relation to the semiconductor substrate.

Assignees

• Maxim Integrated Products

Inventors

• Kelkar Amit S
• Thambidurai Karthik
• Khandekar Viren
• Nguyen Hien D

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title