Additional pessimism removal in static timing analysis
US-2026073110-A1 · Mar 12, 2026 · US
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Kalafala Kerim patents
Kalafala Kerim is listed as an inventor on 118 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kalafala Kerim |
| Total patents | 118 |
| First publication | Oct 29, 2015 |
| Latest publication | Mar 12, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Generating parameters for statistical timing analysis of a circuit
US-2026057160-A1 · Feb 26, 2026 · US
Recommending changes in the design of an integrated circuit using a rules-based analysis of failures
US-12547802-B2 · Feb 10, 2026 · US
Timing-aware fill
US-2025245413-A1 · Jul 31, 2025 · US
Timing constraint auto-creation for integrated circuit testing
US-2025005244-A1 · Jan 2, 2025 · US
Timing analysis for non-scan latches
US-2024386175-A1 · Nov 21, 2024 · US
Location aware timing analysis of a digital integrated circuit
US-2024330556-A1 · Oct 3, 2024 · US
Timing analysis of a digital integrated circuit using intent based timing constraints
US-2024330551-A1 · Oct 3, 2024 · US
Recommending changes in the design of an integrated circuit using a rules-based analysis of failures
US-2024119205-A1 · Apr 11, 2024 · US
Efficient projection based adjustment evaluation in static timing analysis of integrated circuits
US-11017137-B2 · May 25, 2021 · US
Recent patents
Latest publications not already listed above.
Efficient projection based adjustment evaluation in static timing analysis of integrated circuits
US-2021103637-A1 · Apr 8, 2021 · US
Leverage cycle stealing within optimization flows
US-10970447-B2 · Apr 6, 2021 · US
Parallel access to running electronic design automation (EDA) application
US-10929567-B2 · Feb 23, 2021 · US
Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits
US-10902167-B1 · Jan 26, 2021 · US
Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits
US-2021011980-A1 · Jan 14, 2021 · US
Offline analysis of hierarchical electronic design automation derived data
US-10891412-B1 · Jan 12, 2021 · US
Variable accuracy incremental timing analysis
US-10747925-B1 · Aug 18, 2020 · US
Variable accuracy incremental timing analysis
US-2020242205-A1 · Jul 30, 2020 · US
Selection of corners and/or margins using statistical static timing analysis of an integrated circuit
US-10606970-B2 · Mar 31, 2020 · US
Leverage cycle stealing within optimization flows
US-10552562-B2 · Feb 4, 2020 · US
Leverage cycle stealing within optimization flows
US-10540465-B2 · Jan 21, 2020 · US
Dynamic update of macro timing models during higher-level timing analysis
US-2019362043-A1 · Nov 28, 2019 · US
Parallel access to running eda application
US-2019286830-A1 · Sep 19, 2019 · US
Leverage cycle stealing within optimization flows
US-2019286773-A1 · Sep 19, 2019 · US
Parallel access to running electronic design automation (EDA) application
US-10387682-B2 · Aug 20, 2019 · US
Multi-sided variations for creating integrated circuits
US-10380286-B2 · Aug 13, 2019 · US
Multi-sided variations for creating integrated circuits
US-10380289-B2 · Aug 13, 2019 · US
Independently projecting a canonical clock
US-10372851-B2 · Aug 6, 2019 · US
Leverage cycle stealing within optimization flows
US-2019220561-A1 · Jul 18, 2019 · US
Programmable clock division methodology with in-context frequency checking
US-10354046-B2 · Jul 16, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 117 |
| Globalfoundries Inc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F2119/12 | 90 |
| G06F30/3312 | 83 |
| G06F30/398 | 60 |
| G06F17/5081 | 59 |
| G06F30/3315 | 51 |