Recommending changes in the design of an integrated circuit using a rules-based analysis of failures

Patent metadata

Field	Value
Publication number	US-12547802-B2
Application number	US-202217963920-A
Country	US
Kind code	B2
Filing date	Oct 11, 2022
Priority date	Oct 11, 2022
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A computer-implemented method, system and computer program product for recommending design changes in designing a digital integrated circuit. An analysis of the digital integrated circuit being designed is performed, where the result of such an analysis involves violations being identified and stored. A stored violation, such as a cross-domain, cross-hierarchy and multi-cycle violation, may then be analyzed to identify a root cause of the violation using a rule. Such a rule may be used for triaging various failures in the cross-domain, cross-hierarchy and/or multi-cycle violation of the digital integrated circuit. A design change in the design of the digital integrated circuit may then be recommended based on the identified root cause of the violation. In this manner, the root cause of failures are effectively identified in the design of digital integrated circuits using an offline analysis of cross-domain, cross-hierarchy and/or multi-cycle violations using a rules-based approach.

First claim

The invention claimed is:

1 . A computer-implemented method for recommending design changes in designing a digital integrated circuit, the method comprising:
performing an analysis of said digital integrated circuit resulting in a plurality of violations, wherein said analysis comprises performing parametric tests on a design of said digital integrated circuit based on an analysis of a continuous circuit parameter, wherein said parametric tests comprise analyzing continuous circuit variables; storing said plurality of violations, wherein said stored violations comprise metadata which includes parameters that were utilized to determine that a violation had occurred; analyzing one of said stored violations to identify a root cause of said one of said stored violations involving a cross-domain, a cross-hierarchy and a multi-cycle violation using a rule, wherein said rule is targeted for triaging said cross-domain, said cross-hierarchy and said multi-cycle violation that was identified based on said analysis of said digital integrated circuit; and generating a recommendation of a design change in designing said digital integrated circuit for said one of said stored violations based on said identified root cause.

2 . The method as recited in claim 1 , wherein said rule addresses said violation using parameterized thresholds involving both noise and timing data.

3 . The method as recited in claim 1 , wherein said rule addresses said violation involving a path that traverses a hierarchy in said design of said digital integrated circuit.

4 . The method as recited in claim 1 , wherein said rule is parameterized.

5 . The method as recited in claim 1 further comprising:
training a model to create an appropriate rule for identifying a root cause of a particular violation based on parameters and data that were utilized in rendering a decision of a violation; and
creating a rule based on providing said trained model parameters and data of a violation identified from said analysis of said digital integrated circuit.

6 . The method as recited in claim 1 , wherein said continuous circuit variables comprise noise margins, propagation delay, maximum clock frequencies, steady-state current, and transient signal behavior.

7 . The method as recited in claim 1 further comprising:
implementing said design change based on said recommendation, wherein said recommendation is generated based on a data structure listing design recommendations based on identified root causes or a machine learning model trained to recommend a design change of said digital integrated circuit based on a root cause of a violation.

8 . A computer program product for recommending design changes in designing a digital integrated circuit, the computer program product comprising one or more computer readable storage mediums having program code embodied therewith, the program code comprising programming instructions for:
performing an analysis of said digital integrated circuit resulting in a plurality of violations, wherein said analysis comprises performing parametric tests on a design of said digital integrated circuit based on an analysis of a continuous circuit parameter, wherein said parametric tests comprise analyzing continuous circuit variables; storing said plurality of violations, wherein said stored violations comprise metadata which includes parameters that were utilized to determine that a violation had occurred; analyzing one of said stored violations to identify a root cause of said one of said stored violations involving a cross-domain, a cross-hierarchy and a multi-cycle violation using a rule, wherein said rule is targeted for triaging said cross-domain, said cross-hierarchy and said multi-cycle violation that was identified based on said analysis of said digital integrated circuit; and generating a recommendation of a design change in designing said digital integrated circuit for said one of said stored violations based on said identified root cause.

9 . The computer program product as recited in claim 8 , wherein said rule addresses said violation using parameterized thresholds involving both noise and timing data.

10 . The computer program product as recited in claim 8 , wherein said rule addresses said violation involving a path that traverses a hierarchy in said design of said digital integrated circuit.

11 . The computer program product as recited in claim 8 , wherein said rule is parameterized.

12 . The computer program product as recited in claim 8 , wherein the program code further comprises the programming instructions for:
training a model to create an appropriate rule for identifying a root cause of a particular violation based on parameters and data that were utilized in rendering a decision of a violation; and creating a rule based on providing said trained model parameters and data of a violation identified from said analysis of said digital integrated circuit.

13 . The computer program product as recited in claim 8 , wherein said continuous circuit variables comprise noise margins, propagation delay, maximum clock frequencies, steady-state current, and transient signal behavior.

14 . The computer program product as recited in claim 8 , wherein the program code further comprises the programming instructions for:
implementing said design change based on said recommendation, wherein said recommendation is generated based on a data structure listing design recommendations based on identified root causes or a machine learning model trained to recommend a design change of said digital integrated circuit based on a root cause of a violation.

15 . A system, comprising:
a memory for storing a computer program for recommending design changes in designing a digital integrated circuit; and a processor connected to said memory, wherein said processor is configured to execute program instructions of the computer program comprising:
performing an analysis of said digital integrated circuit resulting in a plurality of violations, wherein said analysis comprises performing parametric tests on a design of said digital integrated circuit based on an analysis of a continuous circuit parameter, wherein said parametric tests comprise analyzing continuous circuit variables;
storing said plurality of violations, wherein said stored violations comprise metadata which includes parameters that were utilized to determine that a violation had occurred;
analyzing one of said stored violations to identify a root cause of said one of said stored violations involving a cross-domain, a cross-hierarchy and a multi-cycle violation using a rule, wherein said rule is targeted for triaging said cross-domain, said cross-hierarchy and said multi-cycle violation that was identified based on said analysis of said digital integrated circuit; and
generating a recommendation of a design change in designing said digital integrated circuit for said one of said stored violations based on said identified root cause.

16 . The system as recited in claim 15 , wherein said rule addresses said violation using parameterized thresholds involving both noise and timing data.

17 . The system as recited in claim 15 , wherein said rule addresses said violation involving a path that traverses a hierarchy in said design of said digital integrated circuit.

18 . The system as recited in claim 15 , wherein said rule is parameterized.

19 . The system as recited in claim 15 , wherein the program instructions of the computer program further comprise:
training a model t

Assignees

• IBM

Inventors

• Raghunathan Sheshashayee K
• Gates Charles
• Kalafala Kerim
• Kurtz Steven Joseph
• Davis Morgan D
• Dean Debra
• Cavitt Chris
• Bhat Chaitra M
• Taggart Richard William

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F2119/10

  Noise analysis or noise optimisation · CPC title

• G06F30/31 Primary

  Design entry, e.g. editors specifically adapted for circuit design · CPC title