Timing-aware fill

Patent metadata

Field	Value
Publication number	US-2025245413-A1
Application number	US-202418422319-A
Country	US
Kind code	A1
Filing date	Jan 25, 2024
Priority date	Jan 25, 2024
Publication date	Jul 31, 2025
Grant date	—

Abstract

Embodiments of the present disclosure provide methods, systems, and computer program products for implementing intelligent timing aware metal fill optimization for an IC layout. The disclosed methods enable fill tooling to identify the existing metal tile density and provide timing-aware metal fill insertion to specifically target density requirements and enable effective timing characteristics of signal path nets.

First claim

What is claimed is:

1 . A method comprising:
accessing physical design data for an integrated circuit (IC) layout, wherein the physical design data comprises a netlist comprising active metal shapes of a metal shapes infrastructure forming signal path nets connecting different parts of the IC layout; performing timing-based design rule checking of the physical design data to identify net timing characteristics of the signal path nets and net timing properties of the active metal shapes of the metal shapes infrastructure; and performing shape-based density design rule checking of the metal shapes infrastructure, based on the net timing characteristics and the net timing properties of the active metal shapes, to perform fill insertion of metal fill shapes to satisfy density requirements in the IC layout.

2 . The method of claim 1 , wherein the physical design data further comprises metal fill shapes of the metal shapes infrastructure, and wherein performing timing-based design rule checking of the physical design data further comprises performing timing-based design rule checking of the active metal shapes forming the signal path nets and the metal fill shapes of the metal shapes infrastructure to identify the net timing characteristics of the signal path nets and the net timing properties of the active metal shapes of the metal shapes infrastructure, and to identify metal fill shapes insertion to minimize timing delay to signal paths, and to increase timing delay to signal paths.

3 . The method of claim 1 , wherein performing shape-based density design rule checking of the metal shapes infrastructure further comprises assigning net timing priorities of the active metal shapes forming the signal path nets into the metal shapes infrastructure based on the net timing characteristics of the signal path nets and the net timing properties of the active metal shapes.

4 . The method of claim 1 , wherein the physical design data further comprises metal fill shapes of the metal shapes infrastructure, and wherein performing shape-based density design rule checking of the metal shapes infrastructure includes performing shape-based density design rule checking of the active metal shapes forming the signal path nets and the metal fill shapes.

5 . The method of claim 1 , wherein performing shape-based density design rule checking of the metal shapes infrastructure further comprises performing the fill insertion of metal fill shapes to achieve a predefined minimum density threshold to satisfy density requirements in the IC layout.

6 . The method of claim 1 , wherein performing shape-based density design rule checking of the metal shapes infrastructure further comprises identifying critical signal path nets based on the net timing characteristics of the signal path nets, and performing shape-based density design rule checking of the critical signal path nets first.

7 . The method of claim 6 , wherein performing shape-based density design rule checking of the critical signal path nets first further comprises assigning 3-dimensional track spacings based on timing slack thresholds of the critical signal path nets, and performing the fill insertion of metal fill shapes based on the timing slack thresholds of respective critical signal path nets to achieve a predefined minimum density threshold to satisfy density requirements in the IC layout.

8 . The method of claim 1 , wherein performing shape-based density design rule checking of the metal shapes infrastructure further comprises identifying non-critical signal path nets based on the net timing characteristics of the signal path nets, and performing shape-based density design rule checking of the non-critical signal path nets first.

9 . The method of claim 8 , wherein performing shape-based density design rule checking of the non-critical signal path nets first further comprises assigning 3-dimensional fill zones based on timing slack thresholds of the non-critical signal path nets, and adding metal fill shapes in the 3-dimensional fill zones based on the timing slack thresholds of respective non-critical signal path nets to achieve a predefined minimum density threshold to satisfy density requirements in the IC layout.

10 . The method of claim 1 , wherein performing shape-based density design rule checking of the physical design data further comprises identifying a potential timing impact for each added metal fill shape to build a dynamic approximation of timing impact for the fill insertion of the metal fill shapes.

11 . A system, comprising one or more computer processors; and a memory containing a program which when executed by the one or more computer processors performs an operation, the operation comprising:
accessing physical design data for an integrated circuit (IC) layout, the physical design data comprising a netlist comprising active metal shapes of a metal shapes infrastructure forming signal path nets connecting different parts of the IC layout; performing timing-based design rule checking of the physical design data to identify net timing characteristics of the signal path nets and net timing properties of the active metal shapes of the metal shapes infrastructure; and performing shape-based density design rule checking of the metal shapes infrastructure, based on the net timing characteristics and the net timing properties of the active metal shapes, to perform fill insertion of metal fill shapes to satisfy density requirements in the IC layout.

12 . The system of claim 11 , wherein performing shape-based density design rule checking of the metal shapes infrastructure further comprises assigning net timing priorities of the active metal shapes forming the signal path nets into the metal shapes infrastructure based on the net timing characteristics of the signal path nets and the net timing properties.

13 . The system of claim 11 , wherein performing shape-based density design rule checking of the metal shapes infrastructure further comprises identifying critical signal path nets based on the net timing characteristics of the signal path nets, and performing shape-based density design rule checking of the critical signal path nets first.

14 . The system of claim 13 , wherein performing shape-based density design rule checking of the critical signal path nets first further comprises assigning 3-dimensional track spacings based on timing slack thresholds of the critical signal path nets, and performing the fill insertion of metal fill shapes based on the timing slack thresholds of respective critical signal path nets to achieve a predefined minimum density threshold to satisfy density requirements in the IC layout.

15 . The system of claim 11 , wherein performing shape-based density design rule checking of the metal shapes infrastructure further comprises identifying non-critical signal path nets based on the net timing characteristics of the signal path nets, and performing shape-based density design rule checking of the non-critical signal path nets first.

16 . A computer program product comprising a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to perform an operation comprising:
accessing physical design data for an integrated circuit (IC) layout, the physical design data comprising a netlist comprising active metal shapes of a metal shapes infrastructure forming signal path nets connecting different parts of the IC layout; performing timing-based design rule checking of the physical design data to identify n

Assignees

• IBM

Inventors

• Wolpert David
• Guzowski Matthew T
• Kalafala Kerim
• Allen Robert John
• Rose Ronald Dennis
• Suess Alexander Joel
• Wood Michael Hemsley
• Allen Margaret Annabelle

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title