Offline analysis of hierarchical electronic design automation derived data

Patent metadata

Field	Value
Publication number	US-10891412-B1
Application number	US-202016789912-A
Country	US
Kind code	B1
Filing date	Feb 13, 2020
Priority date	Feb 13, 2020
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

An electronic design automation (EDA) data processing system includes a version graph database and a controller. The version graph database stores a plurality of different versions of graph data sets. Each graph data set corresponds to a respective circuit component located at a given hierarchical level of a semiconductor chip design and each graph data set tagged with a version identifier (ID) indicating the version thereof. The controller determines a hierarchical circuit included in the semiconductor chip and determines a plurality of targeted circuit components that define the hierarchical circuit. The controller determines targeted graph data sets from the versions graph database that correspond to the targeted circuit components, and obtains the targeted graph data sets having matching version IDs such that the targeted graph data sets are the same version.

First claim

What is claimed is:

1. An electronic design automation (EDA) data processing system comprising:
a version graph database configured to store a plurality of different versions of graph data sets, each graph data set corresponding to a respective circuit component located at a given hierarchical level of a semiconductor chip design and each graph data set tagged with a version identifier (ID) indicating the version thereof; and
a controller in signal communication with the version graph database, the controller configured to determine a hierarchical circuit included in the semiconductor chip and to determine a plurality of targeted circuit components that define the hierarchical circuit,
wherein the controller determines targeted graph data sets from the versions graph database that correspond to the targeted circuit components, and obtains the targeted graph data sets having matching version IDs such that the targeted graph data sets are the same version.

2. The EDA data processing system of claim 1 , wherein the controller stitches together the targeted graph data sets to generate a hierarchical graph representing the hierarchical circuit.

3. The EDA data processing system of claim 2 , wherein a first targeted circuit component among the targeted circuit components is located at a first hierarchical level and a second targeted circuit component among the targeted circuit components is located at a second hierarchical level different from the first hierarchical level.

4. The EDA data processing system of claim 3 , wherein the first hierarchical level is a parent level and the second hierarchical level is a child level that is lower than the parent level.

5. The EDA data processing system of claim 3 , wherein the controller performs at least one test diagnostic on the hierarchical graph having the same versions of the targeted graph data sets.

6. The EDA data processing system of claim 5 , wherein the at least one test diagnostic is selected from a group comprising a static timing analysis, a statistical timing analysis, and a power analysis.

7. The EDA data processing system of claim 3 , wherein the controller stores the hierarchical graph having the same versions of the targeted graph data sets in a version graph database.

8. A computer implemented method for diagnosing a semiconductor chip design, the method comprising:
generating a graph data set corresponding to a respective circuit component located at a given hierarchical level of a semiconductor chip design;
tagging the graph data set with a version identifier (ID) indicating a version of the graph data set;
storing, in a version graph database, the graph data set with the version identifier (ID) such that a plurality of different versions of graph data sets are stored in the version graph database;
determining, via a controller, a hierarchical circuit included in the semiconductor chip and determining a plurality of targeted circuit components that define the hierarchical circuit;
determining, via the controller, targeted graph data sets from the versions graph database that correspond to the targeted circuit components, and obtaining, via the controller, the targeted graph data sets having matching version IDs such that the targeted graph data sets are the same version; and
stitching together the targeted graph data sets, via the controller, to generate a hierarchical graph representing the hierarchical circuit.

9. The method of claim 8 , wherein a first targeted circuit component among the targeted circuit components is located at a first hierarchical level and a second targeted circuit component among the targeted circuit components is located at a second hierarchical level different from the first hierarchical level.

10. The method of claim 9 , wherein the first hierarchical level is a parent level and the second hierarchical level is a child level that is lower than the parent level.

11. The method of claim 10 , wherein the controller performs at least one test diagnostic on the hierarchical graph having the same versions of the targeted graph data sets.

12. The method of claim 11 , wherein the at least one test diagnostic is selected from a group comprising a static timing analysis, a statistical timing analysis, and a power analysis.

13. The method of claim 9 , wherein the controller stores the hierarchical graph having the same versions of the targeted graph data sets in a version graph database.

14. A computer program product for diagnosing a semiconductor chip design, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising:
generating a graph data set corresponding to a respective circuit component located at a given hierarchical level of a semiconductor chip design;
tagging the graph data set with a version identifier (ID) indicating a version of the graph data set;
storing, in a version graph database, the graph data set with the version identifier (ID) such that a plurality of different versions of graph data sets are stored in the version graph database;
determining, via a controller, a hierarchical circuit included in the semiconductor chip and determining a plurality of targeted circuit components that define the hierarchical circuit; and
determining, via the controller, targeted graph data sets from the versions graph database that correspond to the targeted circuit components, and obtaining, via the controller, the targeted graph data sets having matching version IDs such that the targeted graph data sets are the same version.

15. The computer program product of claim 14 , further comprising stitching together the targeted graph data sets, via the controller, to generate a hierarchical graph representing the hierarchical circuit.

16. The computer program product of claim 15 , wherein a first targeted circuit component among the targeted circuit components is located at a first hierarchical level and a second targeted circuit component among the targeted circuit components is located at a second hierarchical level different from the first hierarchical level.

17. The computer program product of claim 16 , wherein the first hierarchical level is a parent level and the second hierarchical level is a child level that is lower than the parent level.

18. The computer program product of claim 14 , wherein the controller performs at least one test diagnostic on the hierarchical graph having the same versions of the targeted graph data sets.

19. The computer program product of claim 18 , wherein the at least one test diagnostic is selected from a group comprising a static timing analysis, a statistical timing analysis, and a power analysis.

20. The computer program product of claim 16 , wherein the controller stores the hierarchical graph having the same versions of the targeted graph data sets in a version graph database.

Assignees

• IBM

Inventors

• Raghunathan Sheshashayee K
• Guzowski Thomas S
• Buck Nathan
• Kalafala Kerim
• Dilullo Jack
• Dean Debra

Classifications

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/3315 Primary

  using static timing analysis [STA] · CPC title

• G06F30/31

  Design entry, e.g. editors specifically adapted for circuit design · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F16/9024 Primary

  Graphs; Linked lists (G06F16/9027 takes precedence) · CPC title