Multi-sided variations for creating integrated circuits

Patent metadata

Field	Value
Publication number	US-10380289-B2
Application number	US-201715822513-A
Country	US
Kind code	B2
Filing date	Nov 27, 2017
Priority date	Feb 20, 2017
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

First claim

What is claimed is:

1. A method for creating an integrated circuit with non-linear variations, the method comprising:
identifying, by one or more computer processors, an integrated circuit design;
identifying, by one or more computer processors, a timing model associated with the identified integrated circuit design;
defining, by one or more computer processors, one or more static single sided variables;
defining, by one or more computer processors, one or more regions of one or more of the defined one or more static single sided variables that are treated linearly;
defining, by one or more computer processors, one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables;
identifying, by one or more computer processors, one or more timing paths within the identified integrated circuit design;
performing, by one or more computer processors, a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; and
providing, by one or more computer processors, one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

2. The method of claim 1 , further comprises:
calculating, by one or more computer processors, a variation associated with each of the one or more multi-sided parameters within each of the divided one or more regions;
propagating, by one or more computer processors, each of the one or more multi-sided parameters based on the calculated variation;
performing, by one or more computer processors, maximum operation on each of the calculated variation of the one or more multi-sided parameters;
performing, by one or more computer processors, minimum operations on each of the calculated variation of the one or more multi-sided parameters; and
projecting, by one or more computer processors, to a corner space based on a combination of one or more of: the performed maximum operation and the performed minimum operations.

3. The method of claim 1 , wherein defining one or more regions of one or more of the defined static single sided variables that are treated linearly further comprises:
identifying, by one or more computer processors, a non-linearity within a parameter space associated with the identified integrated circuit design; and
dividing, by one or more computer processors, the identified non-linearity into one or more regions, wherein each of the divided one or more regions identifies a linear space within the parameter space.

4. The method of claim 1 , wherein performing the statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables further comprises:
calculating, by one or more computer processors, one or more sensitivities based on the one or more regions for each of the identified one or more timing paths utilizing the defined one or more multi-sided variables;
identifying, by one or more computer processors, one or more delays with respect to the identified one or more timing paths within the identified integrated circuit design for the defined one or more multi-sided variables from within the identified timing model that identifies the one or more delays via a look-up table by a gate type and a slew/load process, voltage, temperature (PVT) condition; and
generating, by one or more computer processors, canonical forms of the one or more multi-sided variables based on the identified one or more delays and the calculated one or more sensitivities, wherein the canonical forms represent timing quantities that include a mean value and one or more sensitivities to a source of variation.

5. The method of claim 4 further comprises:
projecting, by one or more computer processors, the identified one or more timing paths to each process corner;
creating, by one or more computer processors, a canonical form for the projected one or more timing paths to each process corner;
merging, by one or more computer processors, the created canonical forms to calculate a statistical maximum; and
adjusting, by one or more computer processors, a sensitivity associated with the defined one or more multi-sided variables based on the calculated statistical maximum.

6. The method of claim 1 , wherein the one or more multi-sided parameters are variables in which a canonical form includes a positive variation term and a negative variation term that are mutually exclusive.

7. The method of claim 1 , further comprises:
utilizing, by one or more computer processors, a finite differencing scheme to calculate one or more cross terms.

8. The method of claim 1 , further comprises:
performing, by one or more computer processors, a statistical static timing analysis on the identified timing model associated with the identified integrated circuit design utilizing remaining single-sided variables that are not transformed to multi-sided variables.

9. The method of claim 1 further comprises:
determining, by one or more computer processors, whether the identified integrated circuit design is valid, based on the provided one or more timing quantities; and
responsive to determining the identified integrated circuit design is valid, providing, by one or more computer processors, an indication to create an integrated circuit based on the identified integrated circuit design.

Assignees

• IBM

Inventors

• Allen Robert J
• Buck Nathan C
• Foreman Eric A
• Hemmett Jeffrey G
• Kalafala Kerim
• Schaeffer Gregory M
• Shuma Stephen G
• Sinha Debjit
• Venkateswaran Natesan
• Zolotov Vladimir

Classifications

• G06F30/36 Primary

  Circuit design at the analogue level · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F17/5031 Primary

  Physics · mapped topic