Multi-sided variations for creating integrated circuits

Patent metadata

Field	Value
Publication number	US-10380286-B2
Application number	US-201715436895-A
Country	US
Kind code	B2
Filing date	Feb 20, 2017
Priority date	Feb 20, 2017
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

The computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

First claim

What is claimed is:

1. A computer program product for creating an integrated circuit with non-linear variations, the computer program product comprising:
one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising:
program instructions to identify an integrated circuit design;
program instructions to identify a timing model associated with the identified integrated circuit design;
program instructions to define one or more static single sided variables;
program instructions to define one or more regions of one or more of the defined one or more static single sided variables that are treated linearly;
program instructions to define one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables;
program instructions to identify one or more timing paths within the identified integrated circuit design;
program instructions to perform a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables;
program instructions to provide one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis; and
manufacturing an integrated circuit based on program instructions, wherein the provided one or more timing quantities that are valid.

2. The computer program product of claim 1 , further comprises program instructions, stored on the one or more computer readable storage media, to:
calculate a variation associated with each of the one or more multi-sided parameters within each of the divided one or more regions;
propagate each of the one or more multi-sided parameters based on the calculated variation;
perform maximum operation on each of the calculated variation of the one or more multi-sided parameters;
perform minimum operations on each of the calculated variation of the one or more multi-sided parameters; and
project to a corner space based on a combination of one or more of: the performed maximum operation and the performed minimum operations.

3. The computer program product of claim 1 , wherein defining one or more regions of one or more of the defined static single sided variables that are treated linearly further comprises program instructions, stored on the one or more computer readable storage media, to:
identify a non-linearity within a parameter space associated with the identified integrated circuit design; and
divide the identified non-linearity into one or more regions, wherein each of the divided one or more regions identifies a linear space within the parameter space.

4. The computer program product of claim 1 , wherein performing the statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables further comprises program instructions, stored on the one or more computer readable storage media, to:
calculate one or more sensitivities based on the one or more regions for each of the identified one or more timing paths utilizing the defined one or more multi-sided variables;
identify one or more delays with respect to the identified one or more timing paths within the identified integrated circuit design for the defined one or more multi-sided variables from within the identified timing model that identifies the one or more delays via a look-up table by a gate type and a slew/load process, voltage, temperature (PVT) condition; and
generate canonical forms of the one or more multi-sided variables bases on the identified one or more delays and the calculated one or more sensitivities, wherein the canonical forms represent timing quantities that include a mean value and one or more sensitivities to a source of variation.

5. The computer program product of claim 4 further comprises program instructions, stored on the one or more computer readable storage media, to:
project the identified one or more timing paths to each process corner;
create a canonical form for the projected one or more timing paths to each process corner;
merge the created canonical forms to calculate a statistical maximum; and
adjust a sensitivity associated with the defined one or more multi-sided variables based on the calculated statistical maximum.

6. The computer program product of claim 1 , further comprises program instructions, stored on the one or more computer readable storage media, to:
perform a statistical static timing analysis on the identified timing model associated with the identified integrated circuit design utilizing remaining single-sided variables that are not transformed to multi-sided variables.

7. The computer program product of claim 1 further comprises program instructions, stored on the one or more computer readable storage media, to:
determine whether the identified integrated circuit design is valid, based on the provided one or more timing quantities; and
responsive to determining the identified integrated circuit design is valid, provide an indication to create an integrated circuit based on the identified integrated circuit design.

8. A computer system for creating an integrated circuit with non-linear variations, the computer system comprising:
one or more computer processors, one or more computer readable storage media, and program instructions stored on the computer readable storage media for execution by at least one of the one or more processors, the program instructions comprising:
program instructions to identify an integrated circuit design;
program instructions to identify a timing model associated with the identified integrated circuit design;
program instructions to define one or more static single sided variables;
program instructions to define one or more regions of one or more of the defined one or more static single sided variables that are treated linearly;
program instructions to define one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables;
program instructions to identify one or more timing paths within the identified integrated circuit design;
program instructions to perform a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables;
program instructions to provide one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis; and
manufacturing an integrated circuit based on program instructions, wherein the provided one or more timing quantities that are valid.

9. The computer system of claim 8 , further comprises program instructions, stored on the one or more computer readable storage media, to:
calculate a variation associated with each of the one or more multi-sided parameters within each of the divided one or more regions;
propagate each of the one or more multi-sided parameters based on the calculated variation;
perform maximum operation on each of the calculated variation of the one or more multi-sided parameters;
perform minimum operations on each of the calculated variation of the one or more multi-sided parameters; and
project to a corner space based on a combination of one or more of: the performed maximum operation and the performed minimum operations.

10.

Assignees

• IBM

Inventors

• Allen Robert J
• Buck Nathan C
• Foreman Eric A
• Hemmett Jeffrey G
• Kalafala Kerim
• Schaeffer Gregory M
• Shuma Stephen G
• Sinha Debjit
• Venkateswaran Natesan
• Zolotov Vladimir

Classifications

• G06F30/36 Primary

  Circuit design at the analogue level · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F2217/84

  Physics · mapped topic