Variable accuracy incremental timing analysis

Patent metadata

Field	Value
Publication number	US-10747925-B1
Application number	US-201916257386-A
Country	US
Kind code	B1
Filing date	Jan 25, 2019
Priority date	Jan 25, 2019
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

A system and method of performing variable accuracy incremental timing analysis in integrated circuit development includes generating a timing graph for interconnected components. The timing graph represents each pin as a node and each interconnection as an arc. A first node or arc is selected. First-level timing values are obtained for the first node or arc using a first timing model that provides a first level of accuracy. n timing models with corresponding n levels of accuracy are pre-selected. The first-level timing values are copied as second-level timing values and as timing values for every other one of the n levels of accuracy for the first node or arc. A second node or arc downstream from the first node or arc is selected. Second-level timing values for the second node or arc are obtained using a second timing model that provides a second level of accuracy.

First claim

What is claimed is:

1. A computer-implemented method of performing variable accuracy incremental timing analysis in integrated circuit development, the method comprising:
generating, using a processor, a timing graph for interconnected components, wherein the interconnected components are some or all components of an integrated circuit design, and the timing graph represents each pin as a node and each interconnection as an arc;
selecting a first node or arc of interest;
obtaining, using the processor, first-level timing values for the first node or arc by performing timing analysis using a first timing model, wherein the first timing model provides a corresponding first level of accuracy and n timing models with corresponding n levels of accuracy are pre-selected;
copying, using the processor, the first-level timing values for the first node or arc as second-level timing values for the first node or arc and as timing values for every other one of the n levels of accuracy above the first level of accuracy;
selecting, using the processor, a second node or arc of interest that is downstream from the first node or arc of interest in the timing graph;
obtaining, using the processor, second-level timing values for the second node or arc by performing the timing analysis using a second timing model, wherein the second timing model provides a corresponding second level of accuracy that is higher than the first level of accuracy and the performing the timing analysis at the second node or arc using the second timing model includes using the second-level timing values for the first node or arc; and
providing the integrated circuit design that is finalized using the timing analysis on the timing graph for implementation into an integrated circuit.

2. The computer-implemented method according to claim 1 , further comprising selecting an initial timing model that provides a corresponding initial level of accuracy; computing initial-level timing values for the first node or the arc of interest using the initial timing model; determining that the initial level of accuracy of the initial timing values must be increased; and selecting the first timing model to obtain the first-level timing values for the first node or arc, wherein the first level of accuracy is higher than the initial level of accuracy corresponding with the initial timing model.

3. The computer-implemented method according to claim 2 , wherein the selecting the first timing model following selecting the initial timing model to obtain the timing values for the first node or arc is a result of an iterative process.

4. The computer-implemented method according to claim 1 , further comprising performing a design change to the first node or arc, updating the timing graph and the timing values for the first node or arc based on the design change, and propagating the timing values for the first node or arc at every one of the n levels of accuracy to update the timing values for the second node or arc.

5. The computer-implemented method according to claim 1 , further comprising performing a design change to the first node or arc, updating the timing graph and the timing values for the first node or arc based on the design change, using n separate queues to respectively propagate the timing values at the n levels of accuracy, and initially propagating only the timing values for the first node or arc at a lowest level of accuracy among the n levels of accuracy to determine if a timing check is passed.

6. The computer-implemented method according to claim 1 , wherein the obtaining the timing values for the first node or arc and the obtaining the timing values for the second node or arc includes obtaining delay, slew, arrival time, or timing slack values.

7. The computer-implemented method according to claim 1 , wherein the obtaining the timing values for the first node or arc by performing the timing analysis using the first timing model includes using static timing analysis, and the obtaining the timing values for the second node or arc by performing the timing analysis using the second timing model includes using statistical static timing analysis, or the obtaining the timing values for the first node or arc by performing the timing analysis using the first timing model includes using a non-linear slew model, and the obtaining the timing values for the second node or arc by performing the timing analysis using the second timing model includes using an Elmore delay calculation based on a resistor-capacitor (RC) model.

8. A system to perform variable accuracy incremental timing analysis in integrated circuit development, the system comprising:
a memory device configured to store a timing graph for interconnected components, wherein the interconnected components are some or all components of an integrated circuit design, and the timing graph represents each pin as a node and each interconnection as an arc; and
a processor configured to select a first node or arc of interest, to obtain first-level timing values for the first node or arc by performing timing analysis using a first timing model, wherein the first timing model provides a corresponding first level of accuracy and n timing models with corresponding n levels of accuracy are pre-selected, to copy the first-level timing values for the first node or arc as second-level timing values for the first node or arc and as timing values for every other one of the n levels of accuracy above the first level of accuracy, to select a second node or arc of interest that is downstream from the first node or arc of interest in the timing graph, and to obtain second-level timing values for the second node or arc by performing the timing analysis using a second timing model, wherein the second timing model provides a corresponding second level of accuracy that is higher than the first level of accuracy and the performing the timing analysis as the second node or arc using the second timing model includes using the second-level timing values for the first node or arc, wherein the integrated circuit design that is finalized using the timing analysis on the timing graph is provided for implementation into an integrated circuit.

9. The system according to claim 8 , wherein the processor is further configured to select an initial timing model that provides a corresponding initial level of accuracy; computing initial-level timing values for the first node or the arc of interest using the initial timing model, to determine that the initial level of accuracy of the initial timing values must be increased, and to select the first timing model to obtain the first-level timing values for the first node or arc, wherein the first level of accuracy is higher than the initial level of accuracy corresponding with the initial timing model.

10. The system according to claim 9 , wherein the processor is configured to select the first timing model following selection of the initial timing model to obtain the timing values for the first node or arc in an iterative process.

11. The system according to claim 8 , wherein the processor is further configured to perform a design change to the first node or arc, to update the timing graph and the timing values for the first node or arc based on the design change, and to propagate the timing values for the first node or arc at every one of the n levels of accuracy to update the timing values for the second node or arc.

12. The system according to claim 8 wherein the processor is further configured to perform a design change to the first node or arc, to update the timing graph and the timing values for the first node or arc based on the design change, use n separate queues to respectivel

Assignees

• IBM

Inventors

• Hemmett Jeffrey
• Kalafala Kerim
• Venkateswaran Natesan
• Sinha Debjit
• Foreman Eric
• Peddawad Chaitanya Ravindra

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title