Independently projecting a canonical clock

Patent metadata

Field	Value
Publication number	US-10372851-B2
Application number	US-201715592351-A
Country	US
Kind code	B2
Filing date	May 11, 2017
Priority date	May 11, 2017
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A design and timing model for at least one circuit path of at least a portion of an IC design is loaded into a computer. At least one canonical clock variable associated with the model is defined; it includes at least one source of variation. The computer is used to perform an SSTA of the at least one circuit path, based on the design and timing model and the at least one canonical clock variable, to obtain slack canonical data. A clock period is projected, based on the slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical. Results of the SSTA and the projected clock period are output to determine performance compliance. Efficient operation of the computer is enhanced by analyzing a slack vector in a single timing run, loaded once, and multithreading timing propagation.

First claim

What is claimed is:

1. A method comprising:
loading a design and timing model for at least one circuit path of at least a portion of an integrated circuit design into a computing device;
defining at least one canonical clock variable associated with said design and timing model, wherein said at least one canonical clock variable includes at least one source of variation;
using said computing device to perform a statistical static timing analysis (SSTA) of said at least one circuit path, based on said design and timing model and said at least one canonical clock variable, to obtain slack canonical data;
projecting a clock period, based on said slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical;
outputting results of said statistical static timing analysis (SSTA) and said projected clock period in a form for determining performance compliance of said at least one circuit path of said at least a portion of said integrated circuit design;
determining that said performance compliance of said at least one circuit path of said at least a portion of said integrated circuit design is satisfactory;
responsive to said determining, instantiating said at least one circuit path of said at least a portion of said integrated circuit design into a design structure; and
fabricating a physical integrated circuit including a physical manifestation of said at least one circuit path of said at least a portion of said integrated circuit design, based on said design structure.

2. The method of claim 1 , wherein:
said slack canonical data is characterized in a canonical slack equation comprising a plurality of terms, each of said terms in turn comprising a mean value plus or minus a predetermined number of standard deviations times a corresponding sensitivity;
at least a first one of said plurality of terms corresponds to a cycle time canonical form;
at least a second one of said plurality of terms corresponds to a logic canonical form; and
said clock period is projected to said different space via said predetermined number of standard deviations for said cycle time canonical form being different than said logic canonical form.

3. The method of claim 2 , wherein said at least one canonical clock variable includes a plurality of sources of variation and wherein said cycle time canonical form and said logic canonical form have different ones of said sources of variation.

4. The method of claim 3 , wherein said plurality of sources of variation comprise at least one Gaussian source of variation and at least one non-Gaussian source of variation.

5. The method of claim 2 , wherein:
said canonical slack comprises a canonical clock arrival time term plus a canonical cycle time term less a canonical data arrival time term less a canonical guard time term;
said canonical cycle time term comprises said at least first one of said plurality of terms corresponding to said cycle time canonical form;
said canonical clock arrival term, said canonical guard time term, and said canonical data arrival time term comprise said at least second one of said plurality of terms corresponding to said logic canonical form.

6. The method of claim 1 , further comprising enhancing computational efficiency by projecting said clock period, based on said slack canonical data, such that said cycle time canonical is projected to said different space than said logic canonical, without extra clock timing constraints.

7. The method of claim 1 , wherein said cycle time canonical depends on said at least one non-Gaussian source of variation and said logic canonical depends on said at least one Gaussian source of variation.

8. The method of claim 1 , further comprising enhancing computational efficiency by analyzing a slack vector in a single timing run, loaded once, and multithreading timing propagation.

9. The method of claim 1 , wherein said at least one canonical clock variable which includes said at least one source of variation comprises a subset of a total number of variables in said statistical static timing analysis (SSTA).

10. The method of claim 1 , wherein, during said statistical static timing analysis (SSTA) of said at least one circuit path, said cycle time canonical changes due to downstream slack stealing.

11. The method of claim 1 , further comprising providing a system, wherein the system comprises distinct software modules, each of the distinct software modules being embodied on a computer-readable storage medium, and wherein the distinct software modules comprise a projection engine module, a statistical static timing analysis (SSTA) engine module, and a design fixup engine module;
wherein:
said statistical static timing analysis (SSTA) is carried out by said statistical static timing analysis (SSTA) engine module executing on at least one hardware processor;
said projecting of said clock period is carried out by said projection engine module executing on said at least one hardware processor; and
said outputting of said results is carried out by said design fixup engine module executing on said at least one hardware processor.

12. A non-transitory computer readable medium comprising computer executable instructions which when executed by a computer cause the computer to perform the method of:
loading a design and timing model for at least one circuit path of at least a portion of an integrated circuit design into a computing device;
defining at least one canonical clock variable associated with said design and timing model, wherein said at least one canonical clock variable includes at least one source of variation;
using said computing device to perform a statistical static timing analysis (SSTA) of said at least one circuit path, based on said design and timing model and said at least one canonical clock variable, to obtain slack canonical data;
projecting a clock period, based on said slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical;
outputting results of said statistical static timing analysis (SSTA) and said projected clock period in a form for determining performance compliance of said at least one circuit path of said at least a portion of said integrated circuit design;
determining that said performance compliance of said adjusted at least one circuit path of said at least a portion of said integrated circuit design is satisfactory;
responsive to said determining, instantiating said adjusted at least one circuit path of said at least a portion of said integrated circuit design into a design structure; and
fabricating a physical integrated circuit including a physical manifestation of said adjusted at least one circuit path of said at least a portion of said integrated circuit design, based on said design structure.

13. The non-transitory computer readable medium of claim 12 , wherein:
said slack canonical data is characterized in a canonical slack equation comprising a plurality of terms, each of said terms in turn comprising a mean value plus or minus a predetermined number of standard deviations times a corresponding sensitivity;
at least a first one of said plurality of terms corresponds to a cycle time canonical form;
at least a second one of said plurality of terms corresponds to a logic canonical form; and
said clock period is projected to said different space via said predetermined number of standard deviations for said cycle time canonical form being different than said logic canonical form.

14. The non-transitory computer readable medium of claim 13 , wherein said at least one canonical clock variable includ

Assignees

• IBM

Inventors

• Buck Nathan
• Carey Sean M
• Elmendorf Peter C
• Foreman Eric A
• Hemmett Jeffrey G
• Jackson Lyle
• Kalafala Kerim
• Shuma Stephen G
• Wood Michael H

Classifications

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F2111/08

  Probabilistic or stochastic CAD · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title