Additional pessimism removal in static timing analysis

Patent metadata

Field	Value
Publication number	US-2026073110-A1
Application number	US-202418828109-A
Country	US
Kind code	A1
Filing date	Sep 9, 2024
Priority date	Sep 9, 2024
Publication date	Mar 12, 2026
Grant date	—

Abstract

Embodiments of the invention are directed to a computer-implemented method of analyzing timing constraints of a component-under-design (CUD). The computer-implemented method includes performing an initial iteration of a common path pessimism removal (CPPR) analysis on circuit elements of the CUD. The circuit elements includes inputs and outputs, and the circuit elements further include a transparent circuit element. The computer-implemented method further includes storing an initial list of the inputs and the outputs for which timing was adjusted during the initial iteration; and applying a second iteration of the CPPR analysis to the initial list of the inputs and the outputs.

First claim

What is claimed is:

1 . A computer-implemented method of analyzing timing constraints of a component-under-design (CUD), the computer-implemented method comprising:
performing an initial iteration of a common path pessimism removal (CPPR) analysis on candidate circuit elements of the CUD; wherein the candidate circuit elements comprise inputs and outputs; wherein a subset of the candidate circuit elements comprise a first circuit element and a second circuit element, wherein an ability of the second circuit element to meet timing constraints of the CUD depends on the outputs of the first circuit element; storing an initial list of the inputs and the outputs for which timing performance was adjusted during the initial iteration; and applying a second iteration of the CPPR analysis to the initial list of the inputs and the outputs.

2 . The computer-implemented method of claim 1 , wherein the initial iteration of the CPPR analysis is performed substantially in parallel on each of the candidate circuit elements of the CUD.

3 . The computer-implemented method of claim 1 , wherein the computer-implemented method further comprises, responsive to the second iteration of the CPPR analysis, storing a second list of the inputs and the outputs for which timing performance was adjusted during the second iteration.

4 . The computer-implemented method of claim 3 , wherein the computer-implemented method further comprises, responsive to a determination that a maximum number of iterations of the CPPR analysis have been performed, ending the computer-implemented method.

5 . The computer-implemented method of claim 3 further comprising, responsive to a determination that none of the inputs and none of the outputs received adjusted timing performance during an iteration of the CPPR analysis applied to the candidate circuit elements of the CUD, ending the computer-implemented method.

6 . The computer-implemented method of claim 3 , wherein the first circuit element comprises a transparent circuit element.

7 . The computer-implemented method of claim 6 , wherein the transparent circuit element comprises a transparent latch that is operable to pass data while a clock signal applied to the transparent latch is active.

8 . A computer system comprising a processor system electronically coupled to a memory, wherein the processor system is operable to perform processor system operations operable to analyze timing constraints of a component-under-design (CUD), the processor system operations comprising:
performing an initial iteration of a common path pessimism removal (CPPR) analysis on candidate circuit elements of the CUD; wherein the candidate circuit elements comprise inputs and outputs; wherein a subset of the candidate circuit elements comprise a first circuit element and a second circuit element, wherein an ability of the second circuit element to meet timing constraints of the CUD depends on the outputs of the first circuit element; storing an initial list of the inputs and the outputs for which timing performance was adjusted during the initial iteration; and applying a second iteration of the CPPR analysis to the initial list of the inputs and the outputs.

9 . The computer system of claim 8 , wherein the initial iteration of the CPPR analysis is performed substantially in parallel on each of the candidate circuit elements of the CUD.

10 . The computer system of claim 8 , wherein the processor system operations further comprise, responsive to the second iteration of the CPPR analysis, storing a second list of the inputs and the outputs for which timing performance was adjusted during the second iteration.

11 . The computer system of claim 10 , wherein the processor system operations further comprise, responsive to a determination that a maximum number of iterations of the CPPR analysis have been performed, ending the processor system operations.

12 . The computer system of claim 10 , wherein the processor system operations further comprise, responsive to a determination that none of the inputs and none of the outputs received adjusted timing performance during an iteration of the CPPR analysis applied to the candidate circuit elements of the CUD ending the processor system operations.

13 . The computer system of claim 10 , wherein the first circuit element comprises a transparent circuit element.

14 . The computer system of claim 13 , wherein the transparent circuit element comprises a transparent latch that is operable to pass data while a clock signal applied to the transparent latch is active.

15 . A computer program product comprising a computer readable program stored on a computer readable storage medium, wherein the computer readable program, when executed on a processor system, causes the processor system to analyzing timing constraints of a component-under-design (CUD) by performing processor system operations comprising:
performing an initial iteration of a common path pessimism removal (CPPR) analysis on candidate circuit elements of the CUD; wherein the candidate circuit elements comprise inputs and outputs; wherein a subset of the candidate circuit elements comprise a first circuit element and a second circuit element, wherein an ability of the second circuit element to meet timing constraints of the CUD depends on the outputs of the first circuit element; storing an initial list of the inputs and the outputs for which timing performance was adjusted during the initial iteration; and applying a second iteration of the CPPR analysis to the initial list of the inputs and the outputs.

16 . The computer program product of claim 15 , wherein the initial iteration of the CPPR analysis is performed substantially in parallel on each of the candidate circuit elements of the CUD.

17 . The computer program product of claim 15 , wherein the processor system operations further comprise, responsive to the second iteration of the CPPR analysis, storing a second list of the inputs and the outputs for which timing performance was adjusted during the second iteration.

18 . The computer program product of claim 17 , wherein the processor system operations further comprise, responsive to a determination that a maximum number of iterations of the CPPR analysis have been performed, ending the processor system operations.

19 . The computer program product of claim 17 , wherein the processor system operations further comprise, responsive to a determination that none of the inputs and none of the outputs received adjusted timing performance during an iteration of the CPPR analysis applied to the candidate circuit elements of the CUD, ending the processor system operations.

20 . The computer program product of claim 17 , wherein the first circuit element comprises a transparent circuit element.

21 . The computer program product of claim 20 , wherein the transparent circuit element comprises a transparent latch that is operable to pass data while a clock signal applied to the transparent latch is active.

22 . A computer-implemented method of analyzing timing constraints of a component-under-design (CUD), the computer-implemented method comprising:
performing a common path pessimism removal (CPPR) analysis on candidate circuit elements of the CUD; wherein the candidate circuit elements comprise inputs and outputs; wherein a subset of the candidate circuit elements comprises a first circuit element and a second circuit element, wherein an ability of the seco

Assignees

• IBM

Inventors

• Garg Aryan
• Gupta Hemlata
• Maurya Prabhat Kumar
• Verma Manish
• Kalafala Kerim

Classifications

• G06F30/3312

  Timing analysis · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/3315 Primary

  using static timing analysis [STA] · CPC title