Gallium nitride transistor with a doped region
US-2025063755-A1 · Feb 20, 2025 · US
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Hao Pinghai patents
Hao Pinghai is listed as an inventor on 36 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Hao Pinghai |
| Total patents | 36 |
| First publication | Jan 13, 2015 |
| Latest publication | Feb 20, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Gallium nitride transistor with a doped region
US-12166119-B2 · Dec 10, 2024 · US
Semiconductor devices with selectively doped gate electrode structure
US-2024363748-A1 · Oct 31, 2024 · US
Gallium nitride transistor with a doped region
US-2023369482-A1 · Nov 16, 2023 · US
Gallium nitride transistor with a doped region
US-11769824-B2 · Sep 26, 2023 · US
HEMT wafer probe current collapse screening
US-11067620-B2 · Jul 20, 2021 · US
Gallium nitride transistor with a doped region
US-2021159329-A1 · May 27, 2021 · US
Gallium nitride transistor with a doped region
US-10964803-B2 · Mar 30, 2021 · US
Transistor with multiple GaN-based alloy layers
US-10861943-B2 · Dec 8, 2020 · US
High voltage CMOS with triple gate oxide
US-10714474-B2 · Jul 14, 2020 · US
Recent patents
Latest publications not already listed above.
Transistor with multiple gan-based alloy layers
US-2020185499-A1 · Jun 11, 2020 · US
Gallium nitride transistor with a doped region
US-2020161461-A1 · May 21, 2020 · US
Hemt wafer probe current collapse screening
US-2020064394-A1 · Feb 27, 2020 · US
Recessed solid state apparatuses
US-10312095-B1 · Jun 4, 2019 · US
Recessed solid state apparatuses
US-2019157091-A1 · May 23, 2019 · US
Recessed solid state apparatuses
US-10134596-B1 · Nov 20, 2018 · US
Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
US-9865507-B2 · Jan 9, 2018 · US
Single photomask high precision thin film resistor
US-9842895-B2 · Dec 12, 2017 · US
High voltage cmos with triple gate oxide
US-2017301673-A1 · Oct 19, 2017 · US
High voltage CMOS with triple gate oxide
US-9741718-B2 · Aug 22, 2017 · US
Low-cost cmos structure with dual gate dielectrics and method of forming the cmos structure
US-2016322263-A1 · Nov 3, 2016 · US
Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
US-9431302-B2 · Aug 30, 2016 · US
Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
US-9412668-B2 · Aug 9, 2016 · US
Single photomask high precision thin film resistor
US-2016197135-A1 · Jul 7, 2016 · US
Single photomask high precision thin film resistor
US-9305688-B2 · Apr 5, 2016 · US
Low cost transistors
US-2015325578-A1 · Nov 12, 2015 · US
High voltage cmos with triple gate oxide
US-2015325577-A1 · Nov 12, 2015 · US
Low cost transistors
US-9184163-B1 · Nov 10, 2015 · US
Low-cost cmos structure with dual gate dielectrics and method of forming the cmos structure
US-2015249088-A1 · Sep 3, 2015 · US
Low-cost cmos structure with dual gate dielectrics and method of forming the cmos structure
US-2015249040-A1 · Sep 3, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Texas Instruments Inc | 36 |
| Hao Pinghai | 2 |
| Hu Binghua | 1 |
| Pendharkar Sameer | 1 |
| Mitros Jozef C | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 16 |
| H10D84/85 | 15 |
| H10P30/21 | 14 |
| H10D62/8503 | 12 |
| H10D30/475 | 12 |