Gallium nitride transistor with a doped region

Patent metadata

Field	Value
Publication number	US-10964803-B2
Application number	US-201816194794-A
Country	US
Kind code	B2
Filing date	Nov 19, 2018
Priority date	Nov 19, 2018
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

First claim

What is claimed is:

1. A transistor, comprising:
a gallium nitride (GaN) layer;
a GaN-based alloy layer supported by the gallium nitride layer, the GaN-based alloy layer having a top side;
a drain contact structure, a gate contact structure, and a source contact structure, wherein the drain, gate, and source contact structures are supported by the gallium-based alloy layer; and
a highly-doped region positioned in a drain access region, wherein the highly-doped region is configured to prevent an extension of a depletion region to a drain contact region, the highly doped region positioned within the transistor on a drain side of the gate contact structure only.

2. The transistor of claim 1 , wherein the GaN-based alloy layer comprises Al(X) In(Y)Ga(1-X-Y)N, where X and Y are the concentrations of Aluminum and Indium, respectively.

3. The transistor of claim 1 , wherein the drain contact structure contacts the GaN-based alloy layer on an opposite side of the highly doped region from the gate contact structure.

4. The transistor of claim 1 , wherein the top side is planar between the source contact structure and the drain contact structure and the highly-doped region extends from the top side into the GaN-based alloy layer.

5. The transistor of claim 1 , wherein the highly-doped region is n-doped.

6. A transistor, comprising:
a gallium nitride (GaN) layer;
a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the top side of the GaN layer; and
a first n-doped region positioned in a drain access region between the gate contact structure and the drain contact structure and extending from the top side into the GaN layer, wherein:
the drain contact structure has a first edge nearest the gate contact structure and a second edge opposite the first edge;
the first n-doped region has a first edge nearest the gate contact structure and a second edge opposite the first edge;
the second edge of the first n-doped region is laterally closer to the gate contact structure than the second edge of the drain contact structure such that the drain contact structure extends past the first n-doped region.

7. The transistor of claim 6 further comprising a second n-doped region extending from the top side into the GaN layer.

8. The transistor of claim 7 , wherein the second n-doped region contacts the source contact structure.

9. The transistor of claim 6 further comprising a p-doped GaN layer positioned on the top side, wherein the gate contact structure is positioned on the p-doped GaN layer.

10. The transistor of claim 6 , wherein the GaN-based alloy layer comprises Al(X) In(Y)Ga(1-X-Y)N, where X and Y are the concentrations of Aluminum and Indium, respectively.

11. The transistor of claim 1 , wherein the first n-doped region includes silicon.

Assignees

• Texas Instruments Inc

Inventors

• Lee Dong Seup
• Joh Jungwoo
• Hao Pinghai
• Pendharkar Sameer

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/206

  into Group III-V semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/411

  for FETs · CPC title