Recessed solid state apparatuses

Patent metadata

Field	Value
Publication number	US-10312095-B1
Application number	US-201816163602-A
Country	US
Kind code	B1
Filing date	Oct 18, 2018
Priority date	Nov 21, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

An electronic device, that in various embodiments includes a first semiconductor layer comprising a first group III nitride. A second semiconductor layer is located directly on the first semiconductor layer and comprises a second different group III nitride. A cap layer comprising the first group III nitride is located directly on the second semiconductor layer. A dielectric layer is located over the cap layer and directly contacts the second semiconductor layer through an opening in the cap layer.

First claim

What is claimed is:

1. An electronic device, comprising:
a first semiconductor layer comprising a first group III nitride;
a second semiconductor layer located directly on the first semiconductor layer and comprising a second different group III nitride;
a cap layer located directly on the second semiconductor layer, the cap layer comprising the first group III nitride; and
a dielectric layer located over the cap layer that directly contacts the second semiconductor layer through an opening in the cap layer.

2. The electronic device of claim 1 , wherein the first and second layers form a heterojunction at their interface.

3. The electronic device of claim 1 , wherein the first and second semiconductor layers comprise gallium.

4. The electronic device of claim 1 , wherein the second semiconductor layer comprises aluminum.

5. The electronic device of claim 1 , further comprising an insulating layer between the dielectric layer and the second semiconductor layer, wherein the dielectric layer is located on a surface of an opening within the insulating layer.

6. The electronic device of claim 5 , wherein the insulating layer comprises a first dielectric material and the dielectric layer comprises a different second dielectric material.

7. The electronic device of claim 1 , further comprising a gate layer located over the dielectric layer within the opening.

8. The electronic device of claim 1 , wherein the cap layer and the dielectric layer have about a same thickness within the opening.

9. The electronic device of claim 1 , wherein the cap layer comprises a group V element.

10. The electronic device of claim 1 , further comprising first and second contacts having respective ohmic connections to the cap layer, wherein the opening is located between the first and second contacts.

11. A method, comprising:
providing substrate having a first semiconductor layer comprising a first group III nitride;
forming a second semiconductor layer directly on the first semiconductor layer, the second semiconductor comprising a second different group III nitride;
forming a cap layer directly on the second semiconductor layer, the cap layer comprising the first group III nitride; and
depositing a dielectric layer over the cap layer, the dielectric layer directly contacting the second semiconductor layer through an opening in the cap layer.

12. The method of claim 11 , wherein the first and second layers form a heterojunction at their interface.

13. The method of claim 11 , wherein the first and second semiconductor layers comprise gallium.

14. The method of claim 11 , wherein the second semiconductor layer comprises aluminum.

15. The method of claim 11 , further comprising forming an insulating layer such that the insulating layer is located between the dielectric layer and the second semiconductor layer, wherein the dielectric layer is located on a surface of an opening within the insulating layer.

16. The method of claim 15 , wherein the insulating layer comprises a first dielectric material and the dielectric layer comprises a different second dielectric material.

17. The method of claim 11 , further comprising forming a gate layer over the dielectric layer within the opening.

18. The method of claim 11 , wherein the cap layer and the dielectric layer have about a same thickness within the opening.

19. The method of claim 11 , wherein the cap layer comprises a group V element.

20. The method of claim 11 , further comprising forming first and second contacts having respective ohmic connections to the cap layer, wherein the opening is located between the first and second contacts.

Assignees

• Texas Instruments Inc

Inventors

• Lee Dong Seup
• Kondo Yoshikazu
• Hao Pinghai
• Pendharkar Sameer

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10D64/01358 Primary

  the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material · CPC title

• H01L29/2003

  Electricity · mapped topic

• H01L29/205

  Electricity · mapped topic

• H01L29/518

  Electricity · mapped topic