High voltage CMOS with triple gate oxide

Patent metadata

Field	Value
Publication number	US-9741718-B2
Application number	US-201514803759-A
Country	US
Kind code	B2
Filing date	Jul 20, 2015
Priority date	Oct 28, 2011
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

First claim

What is claimed is:

1. An integrated circuit having a p-channel high-voltage metal oxide semiconductor (MOS) transistor and an n-channel high-voltage MOS transistor, comprising:
a substrate comprising a p-type semiconductor;
an n-type n-channel metal oxide semiconductor (NMOS) drain extension and an n-type NMOS source extension of said n-channel high-voltage MOS transistor;
an n-type p-channel metal oxide semiconductor (PMOS) threshold adjustment region of said p-channel high-voltage MOS transistor, said PMOS threshold adjustment region being electrically coupled to an n-type buried layer;
a high-voltage gate dielectric layer at a top surface of said substrate in said p-channel high-voltage MOS transistor and in said n-channel high-voltage MOS transistor;
a p-type NMOS threshold adjustment region of said n-channel high-voltage MOS transistor;
a PMOS drain extension and a PMOS source extension of said p-channel high-voltage MOS transistor, wherein the PMOS drain extension and PMOS source extension are spaced apart from the PMOS threshold adjustment region; and
a high-voltage PMOS gate of said p-channel high-voltage MOS transistor and a high-voltage NMOS gate of said n-channel high-voltage MOS transistor;
such that:
said high-voltage PMOS gate has a drain-centered closed loop configuration;
said high-voltage PMOS gate does not overlap field oxide;
said high-voltage NMOS gate has a drain-centered closed loop configuration;
said high-voltage NMOS gate does not overlap field oxide;
said PMOS drain extension is free of field oxide;
said PMOS source extension between a PMOS source contact region and said PMOS threshold adjustment region is free of field oxide;
said NMOS drain extension is free of field oxide; and
said NMOS source extension between a NMOS source contact region and said NMOS threshold adjustment region is free of field oxide.

2. The integrated circuit of claim 1 , in which:
said high-voltage gate dielectric layer is 40 to 50 nanometers thick;
an NMOS drain contact region and a metal silicide layer on said NMOS drain contact region are laterally separated from said high-voltage NMOS gate by an NMOS gate-to-drain-contact spacing of 550 to 1000 nanometers;
said NMOS drain extension underlaps said high-voltage NMOS gate by an NMOS drain extension underlap length of 250 to 500 nanometers; and
said NMOS drain extension is laterally separated from said NMOS threshold adjustment region by an NMOS channel depletion spacing of 800 to 1200 nanometers.

3. The integrated circuit of claim 1 , in which:
said high-voltage gate dielectric layer is 55 to 70 nanometers thick;
an NMOS drain contact region and a metal silicide layer on said NMOS drain contact region are laterally separated from said high-voltage NMOS gate by an NMOS gate-to-drain-contact spacing of 700 to 1000 nanometers;
said NMOS drain extension underlaps said high-voltage NMOS gate by an NMOS drain extension underlap length of 250 to 500 nanometers; and
said NMOS drain extension is laterally separated from said NMOS threshold adjustment region by an NMOS channel depletion spacing of 800 to 1200 nanometers.

4. The integrated circuit of claim 1 , in which:
said high-voltage gate dielectric layer is 85 to 100 nanometers thick;
an NMOS drain contact region and a metal silicide layer on said NMOS drain contact region are laterally separated from said high-voltage NMOS gate by an NMOS gate-to-drain-contact spacing of 700 to 1000 nanometers;
said NMOS drain extension underlaps said high-voltage NMOS gate by an NMOS drain extension underlap length of 400 to 750 nanometers;
said NMOS drain extension is laterally separated from said NMOS threshold adjustment region by an NMOS channel depletion spacing of 1.8 to 2.5 microns;
a metal silicide layer on said high-voltage NMOS gate is recessed from said lateral edges of said high-voltage NMOS gate by an NMOS gate silicide recess distance of 300 to 500 nanometers; and
an NMOS drain extension gap of 400 to 600 nanometers is formed in said NMOS drain extension.

5. The integrated circuit of claim 1 , in which:
said high-voltage gate dielectric layer is 40 to 50 nanometers thick;
a PMOS drain contact region and a metal silicide layer on said PMOS drain contact region are laterally separated from said high-voltage PMOS gate by a PMOS gate-to-drain-contact spacing of 400 to 1000 nanometers;
said PMOS drain extension underlaps said high-voltage PMOS gate by a PMOS drain extension underlap length of 250 to 500 nanometers; and
said PMOS threshold adjustment region contacts and underlaps said PMOS drain extension.

6. The integrated circuit of claim 1 , in which:
said high-voltage gate dielectric layer is 55 to 70 nanometers thick;
said PMOS drain contact region and a metal silicide layer on said PMOS drain contact region are laterally separated from said high-voltage PMOS gate by a PMOS gate-to-drain-contact spacing of 600 to 1000 nanometers;
a metal silicide layer on said high-voltage PMOS gate is recessed from said lateral edges of said high-voltage PMOS gate by a PMOS gate silicide recess distance of 300 to 500 nanometers;
said PMOS drain extension is laterally separated from said lateral edge of said high-voltage PMOS gate by a PMOS drain extension to gate spacing of 200 to 400 nanometers; and
said PMOS threshold adjustment region is recessed from said lateral edge of said high-voltage PMOS gate by a PMOS threshold recess of 500 to 1000 nanometers.

7. The integrated circuit of claim 1 , in which:
said high-voltage gate dielectric layer is 85 to 100 nanometers thick;
a PMOS drain contact region and a metal silicide layer on said PMOS drain contact region are laterally separated from said high-voltage PMOS gate by a PMOS gate-to-drain-contact spacing of 800 to 1000 nanometers;
a metal silicide layer on said high-voltage PMOS gate is recessed from said lateral edges of said high-voltage PMOS gate by a PMOS gate silicide recess distance of 300 to 500 nanometers;
said PMOS drain extension is laterally separated from said lateral edge of said high-voltage PMOS gate by a PMOS drain extension to gate spacing of 500 to 700 nanometers; and
said PMOS threshold adjustment region is recessed from said lateral edge of said high-voltage PMOS gate by a PMOS threshold recess of 1.5 to 1.8 microns.

8. An integrated circuit comprising:
a substrate comprising a p-type semiconductor;
a drain-centered high voltage p-channel metal oxide semiconductor (PMOS) transistor having:
a PMOS gate dielectric layer at a top surface of the substrate;
a PMOS gate on the PMOS gate dielectric layer, wherein the PMOS gate does not overlap field oxide;
an n-type PMOS threshold adjustment region, said PMOS threshold adjustment region being electrically coupled to an n-type buried layer;
a PMOS drain extension and a PMOS source extension, wherein the PMOS drain extension and PMOS source extension are spaced apart from the PMOS threshold adjustment region and wherein the PMOS drain extension is free of field oxide; and
a PMOS drain in the PMOS drain extension and an PMOS source in the PMOS source extension, wherein the high-voltage PMOS gate surrounds the PMOS drain, and wherein the PMOS source extension between the PMOS source and the PMOS threshold adjustment region is free of field oxide; and

a drain centered high-voltage n-channel metal oxide semiconductor (NMOS) transistor having:
an n-type NMOS drain extension and an n-type NMOS source extension;
a p-type NMOS threshold adjustment region;
an NMOS drain in the NMOS drain extension and an NMOS source in the NMOS source extension, wherein the NMOS drain extension is free of field oxide and the NMOS source extension between the NMOS source and the NMOS threshold adjustment region is

Assignees

• Texas Instruments Inc

Inventors

• Hu Binghua
• Hao Pinghai
• Pendharkar Sameer
• Sridhar Seetharaman
• Jacobs Jarvis

Classifications

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H01L29/665

  Electricity · mapped topic

• H01L29/41758

  Electricity · mapped topic

• H01L21/761

  Electricity · mapped topic