HEMT wafer probe current collapse screening

Patent metadata

Field	Value
Publication number	US-11067620-B2
Application number	US-201916400336-A
Country	US
Kind code	B2
Filing date	May 1, 2019
Priority date	Aug 21, 2018
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A method includes applying a DC stress condition to a transistor for a predetermined stress time, measuring an impedance of the transistor after the predetermined stress time, and repeating the application of the DC stress condition and the measurement of the impedance until the measured impedance exceeds an impedance threshold or a total stress time exceeds a time threshold, where the DC stress condition includes applying a non-zero drain voltage signal to a drain terminal of the transistor, applying a gate voltage signal to a gate terminal of the transistor, and applying a non-zero source current signal to a source terminal of the transistor.

First claim

What is claimed is:

1. A method, comprising:
applying a DC stress condition to a transistor for a predetermined stress time, the DC stress condition including:
applying a non-zero drain voltage signal to a drain terminal of the transistor,
applying a gate voltage signal to a gate terminal of the transistor, and
applying a non-zero source current signal to a source terminal of the transistor;

measuring an impedance of the transistor after the predetermined stress time; and
repeating the application of the DC stress condition and the measurement of the impedance until a measured impedance exceeds a non-zero impedance threshold or a total stress time exceeds a non-zero time threshold.

2. The method of claim 1 , further comprising:
identifying the transistor as failed if the measured impedance exceeds the non-zero impedance threshold; and
identifying the transistor as passed if the total stress time exceeds the non-zero time threshold.

3. The method of claim 1 , further comprising:
engaging probe pins of a wafer test system with conductive features of a wafer, the conductive features connected to terminals of the transistor; and
applying the DC stress condition from a circuit of the wafer test system to the transistor through the probe pins to the conductive features of the wafer.

4. The method of claim 1 , further comprising:
in response to the measured impedance not exceeding the non-zero impedance threshold and the total stress time not exceeding the non-zero time threshold, increasing the predetermined stress time for each successive repetition of the application of the DC stress condition.

5. The method of claim 1 , wherein measuring the impedance of the transistor includes measuring an on-state drain-source resistance of the transistor.

6. The method of claim 1 , wherein applying the non-zero source current signal to the source terminal of the transistor includes sinking a constant non-zero current from the source terminal of the transistor during the predetermined stress time.

7. The method of claim 6 ,
wherein applying the non-zero drain voltage signal to the drain terminal of the transistor includes applying a constant non-zero drain voltage signal to the drain terminal of the transistor during the predetermined stress time; and
wherein applying the gate voltage signal to the gate terminal of the transistor includes applying a constant gate voltage signal to the gate terminal of the transistor during the predetermined stress time.

8. The method of claim 1 , further comprising:
testing multiple transistors at respective locations of a wafer, including, for each of the transistors:
applying the DC stress condition to the transistor for the predetermined stress time,
measuring the impedance of the transistor after the predetermined stress time, and
repeating the application of the DC stress condition and the measurement of the impedance until a measured impedance exceeds the non-zero impedance threshold or a total stress time exceeds the non-zero time threshold,
identifying the transistor as failed if the measured impedance exceeds the non-zero impedance threshold, and
identifying the transistor as passed if the total stress time exceeds the non-zero time threshold; and

identifying a wafer guard band radius between a first transistor of the multiple transistors at a respective first wafer location identified as passed, and a second transistor of the multiple transistors at a respective second wafer location identified as failed.

9. The method of claim 1 , wherein the transistor is a high electron mobility transistor.

10. A method, comprising:
testing multiple high electron mobility transistors (HEMTs) at respective locations of a wafer, including, for each of HEMT:
applying a DC stress condition to the HEMT for a predetermined stress time,
measuring an impedance of the HEMT after the predetermined stress time, and
repeating the application of the DC stress condition and the measurement of the impedance until a measured impedance exceeds a non-zero impedance threshold or a total stress time exceeds a non-zero time threshold,
identifying the HEMT as failed if the measured impedance exceeds the non-zero impedance threshold, and
identifying the HEMT as passed if the total stress time exceeds the non-zero time threshold;

identifying a wafer guard band radius between a first HEMT of the multiple HEMTs at a first wafer location identified as passed, and a second HEMT of the multiple HEMTs at a second wafer location identified as failed;
slicing the wafer; and
packaging the first HEMT of the multiple HEMTs at the first wafer location identified as passed.

11. The method of claim 10 , wherein applying the DC stress condition to the HEMT includes:
applying a non-zero drain voltage signal to a drain terminal of the HEMT;
applying a gate voltage signal to a gate terminal of the HEMT; and
applying a non-zero source current signal to a source terminal of the HEMT.

12. A wafer test system, comprising:
a current source, including a current source output adapted to be coupled to a source terminal of a transistor of a wafer;
a first voltage source, including a first voltage source output adapted to be coupled to a drain terminal of the transistor;
a second voltage source, including a second voltage source output adapted to be coupled to a gate terminal of the transistor;
an impedance measurement circuit, including respective inputs adapted to be coupled to the source terminal and to the drain terminal of the transistor; and
a controller configured to:
control the current source, the first voltage source, and the second voltage source to apply a DC stress condition to the transistor for a predetermined stress time,
control the impedance measurement circuit to measure an impedance of the transistor after the predetermined stress time, and
control the current source, the first voltage source, the second voltage source, and the impedance measurement circuit to repeat the application of the DC stress condition and the measurement of the impedance until a measured impedance exceeds an impedance threshold or a total stress time exceeds a non-zero time threshold,
identify the transistor as failed if the measured impedance exceeds the non-zero impedance threshold, and
identify the transistor as passed if the total stress time exceeds the non-zero time threshold.

13. The wafer test system of claim 12 , wherein the controller is configured to:
control the current source to generate a non-zero DC source current signal at the current source output for the predetermined stress time, and to control the current source to discontinue the non-zero DC source current signal while the impedance measurement circuit measures the impedance of the transistor;
control the first voltage source to generate a non-zero DC drain voltage signal at the first voltage source output for the predetermined stress time; and
control the second voltage source to generate a DC gate voltage signal at the second voltage source output for the predetermined stress time.

14. The wafer test system of claim 13 , wherein the controller is configured to:
control the first voltage source to generate a second non-zero DC drain voltage signal while the impedance measurement circuit measures the impedance of the transistor; and
control the second voltage source to generate a second DC gate voltage signal while the impedance measurement circuit measures the impedance of the transistor.

15. The wafer test system of claim 12 , further comprising:
a probe card, including:
a first probe pin adapted to be coupled t

Assignees

• Texas Instruments Inc

Inventors

• Lee Dong Seup
• Joh Jungwoo
• Hao Pinghai
• Pendharkar Sameer

Classifications

• G01R27/26

  Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants {; Measuring impedance or related variables} · CPC title

• G01R31/2621 Primary

  for testing field effect transistors, i.e. FET's · CPC title

• G01R31/2642

  Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests · CPC title